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riscv,nemu,trap: fix wrong register number

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Zihao Yu 2023-11-03 16:07:10 +08:00
parent 3ba0c6afd7
commit f198eb6073
1 changed files with 1 additions and 1 deletions
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am/src/riscv/nemu/trap.S
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@ -31,7 +31,7 @@ f(30) f(31)
#define PUSH(n) STORE concat(x, n), (n * XLEN)(sp);
#define POP(n) LOAD concat(x, n), (n * XLEN)(sp);
#define CONTEXT_SIZE ((NR_REGS + 3 + 1) * XLEN)
#define CONTEXT_SIZE ((NR_REGS + 3) * XLEN)
#define OFFSET_SP ( 2 * XLEN)
#define OFFSET_CAUSE ((NR_REGS + 0) * XLEN)
#define OFFSET_STATUS ((NR_REGS + 1) * XLEN)