ysyx-workbench/npc/cmake/ChiselBuild.cmake
xinyangli 5bb66edd2f
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npc,refactor: remove unused components
2024-09-07 15:47:28 +08:00

53 lines
2.2 KiB
CMake

# -- Add an always run target to generate verilog files with sbt/bloop, as we
# don't know if the result files will be different from cmake NOTE: Must
# reconfigure if we add new files in SCALA_CORE directory
file(GLOB_RECURSE SCALA_CORE_SOURCES "${SCALA_CORE}/src/main/scala/*.scala")
file(GLOB_RECURSE SCALA_CORE_RESOURCES "${SCALA_CORE}/src/main/resources/*")
message(STATUS "Found scala source file: ${SCALA_CORE_SOURCES}")
set(CHISEL_DEPENDENCY ${SCALA_CORE_SOURCES} ${SCALA_CORE_RESOURCES}
${SCALA_CORE}/build.sbt)
if(BUILD_USE_BLOOP)
message(STATUS "Building core using bloop")
set(CHISEL_TARGET bloop_${TOPMODULE})
set(CHISEL_TEST_TARGET bloop_${TOPMODULE}_test)
# Export sbt build config to bloop
if(NOT EXISTS ${SCALA_CORE}/.bloop)
execute_process(COMMAND sbt bloopInstall WORKING_DIRECTORY ${SCALA_CORE})
endif()
string(REPLACE " " ";" CHISEL_EMIT_ARGS_LIST ${CHISEL_EMIT_ARGS})
list(TRANSFORM CHISEL_EMIT_ARGS_LIST PREPEND "--args;")
add_custom_command(
OUTPUT ${CHISEL_OUTPUT_TOPMODULE} ${CHISEL_OUTPUT_VERILATOR_CONF}
COMMAND bloop run --no-color root ${CHISEL_EMIT_ARGS_LIST}
WORKING_DIRECTORY ${SCALA_CORE}
DEPENDS ${CHISEL_DEPENDENCY}
COMMAND_EXPAND_LISTS
COMMENT "Run bloop from CMake")
# add_test( NAME bloop_${TOPMODULE}_test COMMAND bloop test WORKING_DIRECTORY
# ${SCALA_CORE} )
else()
message(STATUS "Building core using sbt")
set(CHISEL_TARGET sbt_${TOPMODULE})
set(CHISEL_TEST_TARGET sbt_${TOPMODULE}_test)
add_custom_command(
OUTPUT ${CHISEL_OUTPUT_TOPMODULE} ${CHISEL_OUTPUT_VERILATOR_CONF}
# Try to use native sbt to increase performance when possible
COMMAND ${CMAKE_COMMAND} -E env SBT_NATIVE_CLIENT=true sbt
"run ${CHISEL_EMIT_ARGS}"
WORKING_DIRECTORY ${SCALA_CORE}
DEPENDS ${CHISEL_DEPENDENCY}
VERBATIM
COMMENT "Run sbt from CMake")
add_test(
NAME sbt_${TOPMODULE}_test
COMMAND sbt test
WORKING_DIRECTORY ${SCALA_CORE})
endif()
if(NOT EXISTS ${CHISEL_OUTPUT_TOPMODULE})
# Probably cold build, generate verilog at configure time to produce top
# module file
execute_process(COMMAND sbt "run ${CHISEL_EMIT_ARGS}"
WORKING_DIRECTORY ${SCALA_CORE})
endif()