diff --git a/npc/core/src/main/scala/components/ALU.scala b/npc/core/src/main/scala/components/ALU.scala
index f57de09..17ef367 100644
--- a/npc/core/src/main/scala/components/ALU.scala
+++ b/npc/core/src/main/scala/components/ALU.scala
@@ -94,6 +94,7 @@ class newALU(implicit p: Params) extends Module {
     val b = Input(Vec(SrcBSelect.all.length, UInt(p.XLEN)))
   })
   val out = IO(new Bundle {
+    val isEqual = Output(Bool())
     val result = Output(UInt(p.XLEN))
   })
 
@@ -112,6 +113,7 @@ class newALU(implicit p: Params) extends Module {
   val sll = a << b(5, 0)
   val srl = a >> b(5, 0)
   val sra = a.asSInt >> b(5, 0)
+  out.isEqual := a === b
 
   import OpSelect._