diff --git a/flake.nix b/flake.nix index 6656094..35d3b94 100644 --- a/flake.nix +++ b/flake.nix @@ -17,7 +17,7 @@ }; in { - packages.nemu = pkgs.callPackage ./nemu { am-kernels = self.packages.${system}.am-kernels; }; + packages.nemu = pkgs.callPackage ./nemu {}; packages.am-kernels = crossPkgs.stdenv.mkDerivation rec { pname = "am-kernels"; @@ -44,13 +44,12 @@ ''; buildPhase = '' - AS=$CC make -C tests/cpu-tests BUILD_DIR=$(pwd)/build ARCH=$ARCH + AS=$CC make -C tests/cpu-tests BUILD_DIR=$(pwd)/build ARCH=$ARCH --trace ''; installPhase = '' - mkdir -p $out/share/images $out/share/dump - cp build/riscv32-nemu/*.bin $out/share/images - cp build/riscv32-nemu/*.txt $out/share/dump + mkdir -p $out/bin + cp build/riscv32-nemu/*.bin $out/bin ''; dontFixup = true; @@ -61,15 +60,6 @@ gdb ] ++ builtins.attrValues self.packages.${system}; }; - - devShells.nemu = pkgs.mkShell { - packages = with pkgs; [ - clang-tools - ]; - inputsFrom = [ - self.packages.${system}.nemu - ]; - }; } ); } diff --git a/nemu/src/isa/riscv32/inst.c b/nemu/src/isa/riscv32/inst.c index 9c86937..2a53ba5 100644 --- a/nemu/src/isa/riscv32/inst.c +++ b/nemu/src/isa/riscv32/inst.c @@ -1,17 +1,17 @@ /*************************************************************************************** - * Copyright (c) 2014-2022 Zihao Yu, Nanjing University - * - * NEMU is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan - *PSL v2. You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY - *KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO - *NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * - * See the Mulan PSL v2 for more details. - ***************************************************************************************/ +* Copyright (c) 2014-2022 Zihao Yu, Nanjing University +* +* NEMU is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* +* See the Mulan PSL v2 for more details. +***************************************************************************************/ #include "common.h" #include "local-include/reg.h" @@ -36,8 +36,7 @@ enum { #define immB() do { *imm = SEXT(BITS(i, 31, 31), 1) << 12 | BITS(i, 30, 25) << 5 | BITS(i, 11, 8) << 1 | BITS(i, 7, 7) << 11; } while(0) #define immJ() do { *imm = SEXT(BITS(i, 31, 31), 1) << 20 | BITS(i, 30, 21) << 1 | BITS(i, 20, 20) << 11 | BITS(i, 19, 12) << 12; } while(0) -static void decode_operand(Decode *s, int *rd, word_t *src1, word_t *src2, - word_t *imm, int type) { +static void decode_operand(Decode *s, int *rd, word_t *src1, word_t *src2, word_t *imm, int type) { uint32_t i = s->isa.inst.val; int rs1 = BITS(i, 19, 15); int rs2 = BITS(i, 24, 20); @@ -101,6 +100,8 @@ static int decode_exec(Decode *s) { INSTPAT("0000000 ????? ????? 001 ????? 00100 11", slli , I, R(rd) = src1 << imm); INSTPAT("0000000 ????? ????? 101 ????? 00100 11", srli , I, R(rd) = src1 >> imm); INSTPAT("0100000 ????? ????? 101 ????? 00100 11", srai , I, R(rd) = (sword_t)src1 >> (imm & 0x01F)); + + INSTPAT("0000000 ????? ????? 000 ????? 01100 11", add , R, R(rd) = src1 + src2); INSTPAT("0100000 ????? ????? 000 ????? 01100 11", sub , R, R(rd) = src1 - src2); INSTPAT("0000000 ????? ????? 001 ????? 01100 11", sll , R, R(rd) = src1 << src2); @@ -113,17 +114,6 @@ static int decode_exec(Decode *s) { INSTPAT("0000000 ????? ????? 111 ????? 01100 11", and , R, R(rd) = src1 & src2); INSTPAT("0000000 00001 00000 000 00000 11100 11", ebreak , N, NEMUTRAP(s->pc, R(10))); // R(10) is $a0 - - // "M" - INSTPAT("0000001 ????? ????? 000 ????? 01100 11", mul , R, R(rd) = src1 * src2); - INSTPAT("0000001 ????? ????? 001 ????? 01100 11", mulh , R, R(rd) = (int64_t)(sword_t)src1 * (sword_t)src2 >> 32); - INSTPAT("0000001 ????? ????? 010 ????? 01100 11", mulhsu , R, R(rd) = (int64_t)(sword_t)src1 * (uint64_t)src2 >> 32); - INSTPAT("0000001 ????? ????? 011 ????? 01100 11", mulhu , R, R(rd) = (uint64_t)src1 * (uint64_t)src2 >> 32); - INSTPAT("0000001 ????? ????? 100 ????? 01100 11", div , R, R(rd) = (sword_t)src1 / (sword_t)src2); - INSTPAT("0000001 ????? ????? 101 ????? 01100 11", divu , R, R(rd) = src1 / src2); - INSTPAT("0000001 ????? ????? 110 ????? 01100 11", rem , R, R(rd) = (sword_t)src1 % (sword_t)src2); - INSTPAT("0000001 ????? ????? 111 ????? 01100 11", remu , R, R(rd) = src1 % src2); - INSTPAT("??????? ????? ????? ??? ????? ????? ??", inv , N, INV(s->pc)); INSTPAT_END(); diff --git a/npc/CMakeLists.txt b/npc/CMakeLists.txt index db9d0a1..ef78ddd 100644 --- a/npc/CMakeLists.txt +++ b/npc/CMakeLists.txt @@ -1,6 +1,6 @@ cmake_minimum_required(VERSION 3.20) -project(flow) +project(npc) set (CMAKE_CXX_STANDARD 11) cmake_policy(SET CMP0144 NEW) @@ -17,7 +17,7 @@ find_package(verilator REQUIRED) find_library(NVBOARD_LIBRARY NAMES nvboard) find_path(NVBOARD_INCLUDE_DIR NAMES nvboard.h) -set(TOPMODULES "Flow") +set(TOPMODULES "Switch" "Keyboard") foreach(TOPMODULE IN LISTS TOPMODULES) @@ -58,7 +58,7 @@ foreach(TOPMODULE IN LISTS TOPMODULES) file(GLOB_RECURSE SOURCES csrc_nvboard/${TOPMODULE}/*.cpp) add_executable(V${TOPMODULE}_nvboard ${SOURCES} ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/auto_bind.cpp) - verilate(V${TOPMODULE}_nvboard TRACE THREADS + verilate(V${TOPMODULE}_nvboard TRACE COVERAGE THREADS TOP_MODULE ${TOPMODULE} PREFIX V${TOPMODULE} SOURCES ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc/${TOPMODULE}.v) diff --git a/npc/constr/Flow.nxdc b/npc/constr/Flow.nxdc deleted file mode 100644 index 7f82796..0000000 --- a/npc/constr/Flow.nxdc +++ /dev/null @@ -1,3 +0,0 @@ -top=Flow - -io_clock(LD0) diff --git a/npc/core/build.sbt b/npc/core/build.sbt index e04b603..792a764 100644 --- a/npc/core/build.sbt +++ b/npc/core/build.sbt @@ -2,15 +2,14 @@ ThisBuild / scalaVersion := "2.13.12" ThisBuild / version := "0.1.0" -val chiselVersion = "6.2.0" +val chiselVersion = "5.1.0" lazy val root = (project in file(".")) .settings( - name := "flow", + name := "ChiselLearning", libraryDependencies ++= Seq( "org.chipsalliance" %% "chisel" % chiselVersion, - "edu.berkeley.cs" %% "chiseltest" % "6.0.0" % "test", - "com.chuusai" %% "shapeless" % "2.3.3" + "edu.berkeley.cs" %% "chiseltest" % "5.0.2" % "test" ), scalacOptions ++= Seq( "-language:reflectiveCalls", @@ -20,4 +19,4 @@ lazy val root = (project in file(".")) "-Ymacro-annotations", ), addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full), - ) + ) \ No newline at end of file diff --git a/npc/core/src/main/scala/ALU.scala b/npc/core/src/main/scala/ALU.scala index 70f0fea..65ade3e 100644 --- a/npc/core/src/main/scala/ALU.scala +++ b/npc/core/src/main/scala/ALU.scala @@ -1,63 +1,34 @@ -package flow.components +package npc.util import chisel3._ import chisel3.util._ -import shapeless.{HNil, ::} -class ALUControlInterface extends Bundle { - object OpSelect extends ChiselEnum { - val aOpAdd, aOpSub, aOpNot, aOpAnd, aOpOr, aOpXor, aOpSlt, aOpEq, aOpNop = Value - } - object SrcSelect extends ChiselEnum { - val aSrcRs1, aSrcImm = Value - } - val op = Input(OpSelect()) - val src = Input(SrcSelect()) - - type CtrlTypes = OpSelect.Type :: SrcSelect.Type :: HNil - def ctrlBindPorts: CtrlTypes = { - op :: src :: HNil - } -} - -class ALU[T <: UInt](tpe: T) extends Module { - val control = IO(new ALUControlInterface) - val in = IO(new Bundle { - val a = Input(Vec(control.SrcSelect.all.length, tpe)) - val b = Input(tpe) - }) - val out = IO(new Bundle { - val result = Output(tpe) +class ALUGenerator(width: Int) extends Module { + require(width >= 0) + val io = IO(new Bundle { + val a = Input(UInt(width.W)) + val b = Input(UInt(width.W)) + val op = Input(UInt(4.W)) + val out = Output(UInt(width.W)) }) - val a = in.a(control.src.asUInt) + val adder_b = (Fill(width, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub + val add = io.a + adder_b + val and = io.a & io.b + val not = ~io.a + val or = io.a | io.b + val xor = io.a ^ io.b + val slt = io.a < io.b + val eq = io.a === io.b - // val adder_b = (Fill(tpe.getWidth, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub - val add = a + in.b - val sub = a - in.b - val and = a & in.b - val not = ~a - val or = a | in.b - val xor = a ^ in.b - val slt = a < in.b - val eq = a === in.b - - import control.OpSelect._ - - out.result := MuxLookup(control.op, 0.U)(Seq( - aOpAdd -> add, - aOpSub -> sub, - aOpNot -> not, - aOpAnd -> and, - aOpOr -> or, - aOpXor -> xor, - aOpSlt -> slt, - aOpEq -> eq + io.out := MuxLookup(io.op, 0.U)(Seq( + 0.U -> add, + 1.U -> add, // add with b reversed + 2.U -> not, + 3.U -> and, + 4.U -> or, + 5.U -> xor, + 6.U -> slt, + 7.U -> eq, )) } - -object ALU { - def apply[T <: UInt](tpe: T): ALU[T] = { - Module(new ALU(tpe)) - } -} diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala index 1ede7e1..c06bc8e 100644 --- a/npc/core/src/main/scala/Main.scala +++ b/npc/core/src/main/scala/Main.scala @@ -1,129 +1,33 @@ -package flow +package npc -import scala.reflect.runtime.universe._ import chisel3._ import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse} -import chisel3.util.{SRAM} -import chisel3.util.experimental.decode.{decoder, TruthTable} import chisel3.stage.ChiselOption -import chisel3.util.log2Ceil -import chisel3.util.BitPat -import chisel3.util.Enum -import chisel3.experimental.prefix -import shapeless.{HNil, ::} -import shapeless.HList -import shapeless.ops.coproduct.Prepend -import chisel3.util.{ BinaryMemoryFile, HexMemoryFile } +import npc.util.KeyboardSegController -object RV32Inst { - private val bp = BitPat - val addi = this.bp("b???????_?????_?????_000_?????_00100_11") - val inv = this.bp("b???????_?????_?????_???_?????_?????_??") +class Switch extends Module { + val io = IO(new Bundle { + val sw = Input(Vec(2, Bool())) + val out = Output(Bool()) + }) + + io.out := io.sw(0) ^ io.sw(1) } -class PcControl(width: Int) extends Bundle { - object SrcSelect extends ChiselEnum { - val pPC, pExeResult = Value - } - val srcSelect = Output(SrcSelect()) +import npc.util.{PS2Port, KeyboardController, SegControllerGenerator} + +class Keyboard extends Module { + val io = IO(new Bundle { + val ps2 = PS2Port() + val segs = Output(Vec(8, UInt(8.W))) + }) + + val seg_handler = Module(new KeyboardSegController) + val keyboard_controller = Module(new KeyboardController) + + seg_handler.io.keycode <> keyboard_controller.io.out + + keyboard_controller.io.ps2 := io.ps2 + io.segs := seg_handler.io.segs } -import flow.components.{RegControl, PcControlInterface, ALUControlInterface} -class Control(width: Int) extends Module { - val inst = IO(Input(UInt(width.W))) - - val reg = IO(Flipped(new RegControl)) - val pc = IO(Flipped(new PcControlInterface)) - val alu = IO(Flipped(new ALUControlInterface)) - - // TODO: Add .ctrlTypes together instead of writing them by hand. - type T = - Bool :: reg.WriteSelect.Type :: pc.SrcSelect.Type :: alu.OpSelect.Type :: alu.SrcSelect.Type :: HNil - val dst: T = reg.ctrlBindPorts ++ pc.ctrlBindPorts ++ alu.ctrlBindPorts - - val dstList = dst.toList - val reversePrefixSum = dstList.scanLeft(0)(_ + _.getWidth).reverse - val slices = reversePrefixSum.zip(reversePrefixSum.tail) - - import reg.WriteSelect._ - import pc.SrcSelect._ - import alu.OpSelect._ - import alu.SrcSelect._ - import RV32Inst._ - val ControlMapping: Array[(BitPat, T)] = Array( - // Regs :: PC :: Exe - // writeEnable :: writeSelect :: srcSelect :: - (addi, true.B :: rAluOut :: pStaticNpc :: aOpAdd :: aSrcImm :: HNil), - ) - val default = BitPat.dontCare(dstList.map(_.getWidth).reduce(_ + _)) - - def toBits(t: T): BitPat = { - val list: List[Data] = t.toList - list.map(x => BitPat(x.litValue.toInt.U(x.getWidth.W))).reduceLeft(_ ## _) - } - val out = decoder( - inst, - TruthTable(ControlMapping.map(it => (it._1 -> toBits(it._2))), default)) - val srcList = slices.map(s => out(s._1 - 1, s._2)) - - srcList - .zip(dstList.reverse) - .foreach({ case (src, dst) => - dst := src.asTypeOf(dst) - }) -} - -import flow.components.{RegisterFile, RegFileInterface, ProgramCounter, ALU} -import chisel3.util.experimental.loadMemoryFromFileInline -class Flow extends Module { - val dataType = UInt(32.W) - - val ram = SRAM( - size = 1024, - tpe = dataType, - numReadPorts = 2, - numWritePorts = 1, - numReadwritePorts = 0, - memoryFile = HexMemoryFile("./resource/addi.txt") - ) - val control = Module(new Control(32)) - val reg = RegisterFile(32, dataType, 2, 2) - val pc = Module(new ProgramCounter(dataType)) - val alu = Module(new ALU(dataType)) - - ram.readPorts(0).enable := true.B - ram.readPorts(0).address := pc.out - 0x80000000L.U - val inst = ram.readPorts(0).data - - import control.pc.SrcSelect._ - - pc.in.pcSrcs(pStaticNpc.litValue.toInt) := pc.out + 4.U - pc.in.pcSrcs(pBranchResult.litValue.toInt) := alu.out.result - - control.inst := inst - reg.control <> control.reg - pc.control <> control.pc - alu.control <> control.alu - - import control.reg.WriteSelect._ - reg.in.writeData(rAluOut.litValue.toInt) := alu.out.result - // TODO: Read address in load command goes here - ram.readPorts(1).enable := false.B - ram.readPorts(1).address := 0.U - reg.in.writeData(rMemOut.litValue.toInt) := ram.readPorts(1).data - reg.in.writeAddr := inst(11, 7) - reg.in.rs(0) := inst(19, 15) - reg.in.rs(1) := inst(24, 20) - - // TODO: Memory write goes here - ram.writePorts(0).address := 1.U - ram.writePorts(0).data := 1.U - ram.writePorts(0).enable := false.B - - import control.alu.SrcSelect._ - alu.in.a(aSrcRs1.litValue.toInt) := reg.out.src(0) - alu.in.a(aSrcImm.litValue.toInt) := inst(31, 20) - alu.in.b := reg.out.src(1) - - dontTouch(control.out) -} diff --git a/npc/core/src/main/scala/ProgramCounter.scala b/npc/core/src/main/scala/ProgramCounter.scala deleted file mode 100644 index bfb3e1b..0000000 --- a/npc/core/src/main/scala/ProgramCounter.scala +++ /dev/null @@ -1,39 +0,0 @@ -package flow.components -import chisel3._ -import chisel3.util.{Valid, log2Ceil} -import chisel3.util.MuxLookup -import shapeless.{HNil, ::} - -class PcControlInterface extends Bundle { - object SrcSelect extends ChiselEnum { - val pStaticNpc, pBranchResult = Value - } - - val srcSelect = Input(SrcSelect()) - - type CtrlTypes = SrcSelect.Type :: HNil - def ctrlBindPorts: CtrlTypes = { - srcSelect :: HNil - } -} - -class ProgramCounter[T <: Data](tpe: T) extends Module { - - val control = IO(new PcControlInterface) - val in = IO(new Bundle { - val pcSrcs = Input(Vec(control.SrcSelect.all.length, tpe)) - }) - val out = IO(Output(tpe)) - - private val pc = RegInit(0x80000000L.U) - - pc := in.pcSrcs(control.srcSelect.asUInt) - out := pc -} - -object ProgramCounter { - def apply[T <: Data](tpe: T): ProgramCounter[T] = { - val pc = Module(new ProgramCounter(tpe)) - pc - } -} diff --git a/npc/core/src/main/scala/RegisterFile.scala b/npc/core/src/main/scala/RegisterFile.scala index 509ceaa..fbf8a94 100644 --- a/npc/core/src/main/scala/RegisterFile.scala +++ b/npc/core/src/main/scala/RegisterFile.scala @@ -1,86 +1,25 @@ -package flow.components +package npc.util import chisel3._ -import chisel3.util.log2Ceil -import chisel3.util.UIntToOH -import chisel3.util.MuxLookup -import shapeless.{ HNil, :: } -class RegControl extends Bundle { - object WriteSelect extends ChiselEnum { - val rAluOut, rMemOut = Value - } - - val writeEnable = Input(Bool()) - val writeSelect = Input(WriteSelect()) - - type CtrlTypes = Bool :: WriteSelect.Type :: HNil - def ctrlBindPorts: CtrlTypes = { - writeEnable :: writeSelect :: HNil - } -} - -class RegFileData[T <: Data](size:Int, tpe: T, numReadPorts: Int, numWritePorts: Int) extends Bundle { - val write = new Bundle { - val addr = Input(UInt(size.W)) - val data = Vec(numWritePorts, Input(tpe)) - } - val read = Vec(numReadPorts, new Bundle { - val rs = Input(UInt(size.W)) - val src = Output(tpe) +class RegisterFile(readPorts: Int) extends Module { + require(readPorts >= 0) + val io = IO(new Bundle { + val writeEnable = Input(Bool()) + val writeAddr = Input(UInt(5.W)) + val writeData = Input(UInt(32.W)) + val readAddr = Input(Vec(readPorts, UInt(5.W))) + val readData = Output(Vec(readPorts, UInt(32.W))) }) -} -class RegFileInterface[T <: Data](size: Int, tpe: T, numReadPorts: Int, numWritePorts: Int) extends Bundle { - val control = new RegControl - // val data = new RegFileData(size, tpe, numReadPorts, numWritePorts) - val in = new Bundle { - val writeAddr = Input(UInt(size.W)) - val writeData = Input(Vec(numWritePorts, tpe)) - val rs = Input(Vec(numReadPorts, UInt(size.W))) - } - val out = new Bundle { - val src = Output(Vec(numReadPorts, tpe)) - } -} - -class RegisterFileCore[T <: Data](size: Int, tpe: T, numReadPorts: Int) extends Module { - require(numReadPorts >= 0) - val writePort = IO(new Bundle { - val enable = Input(Bool()) - val addr = Input(UInt(log2Ceil(size).W)) - val data = Input(tpe) - }) - val readPorts = IO(Vec(numReadPorts, new Bundle { - val addr = Input(UInt(log2Ceil(size).W)) - val data = Output(tpe) - })) - - val regFile = RegInit(VecInit(Seq.fill(size)(0.U(tpe.getWidth.W)))) - val writeAddrOH = UIntToOH(writePort.addr) - for ((reg, i) <- regFile.zipWithIndex.tail) { - reg := Mux(writeAddrOH(i) && writePort.enable, writePort.data, reg) + val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W)))) + for (i <- 1 until 32) { + regFile(i) := regFile(i) } + regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr)) regFile(0) := 0.U - for (readPort <- readPorts) { - readPort.data := regFile(readPort.addr) - } - dontTouch(regFile) -} - -object RegisterFile { - def apply[T <: Data](size: Int, tpe: T, numReadPorts: Int, numWritePorts: Int): RegFileInterface[T] = { - val core = Module(new RegisterFileCore(size, tpe, numReadPorts)) - val _out = Wire(new RegFileInterface(size, tpe, numReadPorts, numWritePorts)) - val clock = core.clock - for (i <- 0 until numReadPorts) { - core.readPorts(i).addr := _out.in.rs(i) - _out.out.src(i) := core.readPorts(i).data - } - core.writePort.addr := _out.in.writeAddr - core.writePort.data := _out.in.writeData(_out.control.writeSelect.asUInt) - core.writePort.enable := _out.control.writeEnable - _out + for (i <- 0 until readPorts) { + io.readData(i) := regFile(io.readAddr(i)) } } diff --git a/npc/core/src/test/scala/Main.scala b/npc/core/src/test/scala/Main.scala index 0cab4ef..c9c093e 100644 --- a/npc/core/src/test/scala/Main.scala +++ b/npc/core/src/test/scala/Main.scala @@ -1,47 +1,105 @@ -package flow +package npc import chisel3._ import chiseltest._ import org.scalatest.freespec.AnyFreeSpec import chiseltest.simulator.WriteVcdAnnotation -import flow.Flow +import npc.util._ -class RV32CPUSpec extends AnyFreeSpec with ChiselScalatestTester { - "MemoryFile" - { - "correctly load" in { - import chisel3.util.{SRAM, SRAMInterface, HexMemoryFile} - class UserMem extends Module { - val io = IO(new SRAMInterface(1024, UInt(32.W), 1, 1, 0)) - val memoryFile = HexMemoryFile("../resource/addi.txt") - io :<>= SRAM( - size = 1024, - tpe = UInt(32.W), - numReadPorts = 1, - numWritePorts = 1, - numReadwritePorts = 0, - memoryFile = memoryFile - ) - - val read = io.readPorts(0).data - printf(cf"memoryFile=$memoryFile, readPort=$read%x\n") - } - test(new UserMem).withAnnotations(Seq(WriteVcdAnnotation)) { c => - c.io.readPorts(0).enable.poke(true.B) - c.io.writePorts(0).enable.poke(false.B) - c.io.writePorts(0).address.poke(0.U) - c.io.writePorts(0).data.poke(0.U) - for (i <- 0 until 32) { - c.io.readPorts(0).address.poke(i.U) +class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester { + "RegisterFile should work" - { + "with 2 read ports" in { + test(new RegisterFile(2)) { c => + def readExpect(addr: Int, value: Int, port: Int = 0): Unit = { + c.io.readAddr(port).poke(addr.U) + c.io.readData(port).expect(value.U) + } + def write(addr: Int, value: Int): Unit = { + c.io.writeEnable.poke(true.B) + c.io.writeData.poke(value.U) + c.io.writeAddr.poke(addr.U) c.clock.step(1) + c.io.writeEnable.poke(false.B) + } + // everything should be 0 on init + for (i <- 0 until 32) { + readExpect(i, 0, port = 0) + readExpect(i, 0, port = 1) + } + + // write 5 * addr + 3 + for (i <- 0 until 32) { + write(i, 5 * i + 3) + } + + // check that the writes worked + for (i <- 0 until 32) { + readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2) } } } } - "should compile" in { - test(new Flow) { c => - c.clock.step(1) +} + +class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester { + "With 32 width, " - { + val neg = (x: BigInt) => BigInt("FFFFFFFF", 16) - x + 1 + val not = (x: BigInt) => x ^ BigInt("FFFFFFFF", 16) + val mask = BigInt("FFFFFFFF", 16) + val oprands: List[(BigInt, BigInt)] = List( + (5, 3), (101010, 101010), (0xFFFFFFFCL, 0xFFFFFFFFL), (4264115, 2) + ) + val operations: Map[Int, (BigInt, BigInt) => BigInt] = Map( + 0 -> ((a: BigInt, b: BigInt) => (a + b) & mask), + 1 -> ((a: BigInt, b: BigInt) => (a + neg(b)) & mask), + 2 -> ((a, _) => not(a)), + 3 -> (_ & _), + 4 -> (_ | _), + 5 -> (_ ^ _), + 6 -> ((a, b) => if (a < b) 1 else 0), + 7 -> ((a, b) => if (a == b) 1 else 0), + ) + val validate = (c: ALUGenerator,op: Int, oprands: List[(BigInt, BigInt)]) => { + c.io.op.poke(op.U) + oprands.foreach({ case (a, b) => + c.io.a.poke(a.U) + c.io.b.poke(b.U) + c.io.out.expect(operations(op)(a, b)) + }) + } + "add should work" in { + test(new ALUGenerator(32)) { c => validate(c, 0, oprands) } + } + "sub should work" - { + "with positive result" in { + test(new ALUGenerator(32)) { c => + validate(c, 1, oprands.filter({case (a, b) => a >= b})) + } + } + "with negative result" in { + test(new ALUGenerator(32)) { c => + validate(c, 1, oprands.filter({case (a, b) => a < b})) + } + } + } + "not should work" in { + test(new ALUGenerator(32)) { c => validate(c, 2, oprands) } + } + "and should work" in { + test(new ALUGenerator(32)) { c => validate(c, 3, oprands) } + } + "or should work" in { + test(new ALUGenerator(32)) { c => validate(c, 4, oprands) } + } + "xor should work" in { + test(new ALUGenerator(32)) { c => validate(c, 5, oprands) } + } + "compare should work" in { + test(new ALUGenerator(32)) { c => validate(c, 6, oprands) } + } + "equal should work" in { + test(new ALUGenerator(32)) { c => validate(c, 7, oprands) } } } - } diff --git a/npc/core/src/test/scala/RegisterFile.scala b/npc/core/src/test/scala/RegisterFile.scala deleted file mode 100644 index ebc59ee..0000000 --- a/npc/core/src/test/scala/RegisterFile.scala +++ /dev/null @@ -1,81 +0,0 @@ -package flow - -import chisel3._ -import chiseltest._ -import org.scalatest.freespec.AnyFreeSpec -import chiseltest.simulator.WriteVcdAnnotation - -import flow.components._ -class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester { - "RegisterFileCore" - { - "register 0 is always 0" in { - test(new RegisterFileCore(32, UInt(32.W), 2)) { c => - c.readPorts(0).addr.poke(0) - c.readPorts(1).addr.poke(0) - c.writePort.enable.poke(true) - c.writePort.addr.poke(0) - c.writePort.data.poke(0x1234) - - c.readPorts(0).data.expect(0) - c.readPorts(1).data.expect(0) - c.clock.step(2) - c.readPorts(0).data.expect(0) - c.readPorts(1).data.expect(0) - } - } - "register other than 0 can be written" in { - test(new RegisterFileCore(32, UInt(32.W), 2)) { c => - import scala.util.Random - val r = new Random() - for (i <- 1 until 32) { - val v = r.nextLong() & 0xFFFFFFFFL - c.readPorts(0).addr.poke(i) - c.writePort.enable.poke(true) - c.writePort.addr.poke(i) - c.writePort.data.poke(v) - - c.clock.step(1) - c.readPorts(0).data.expect(v) - } - } - } - } - "RegisterInterface" - { - class Top extends Module { - val io = IO(new RegFileInterface(32, UInt(32.W), 2, 2)) - val rf = RegisterFile(32, UInt(32.W), 2, 2) - io :<>= rf - } - "write" in { - test(new Top).withAnnotations(Seq(WriteVcdAnnotation)) { c => - import c.io.control.WriteSelect._ - val writePort = rAluOut.litValue.toInt - c.io.control.writeEnable.poke(true) - c.io.control.writeSelect.poke(rAluOut) - c.io.in.writeAddr.poke(5) - c.io.in.writeData(writePort).poke(0xcdef) - c.io.in.rs(0).poke(5) - c.clock.step(1) - c.io.out.src(0).expect(0xcdef) - } - } - "no data is written when not enabled" in { - test(new Top).withAnnotations(Seq(WriteVcdAnnotation)) { c => - import c.io.control.WriteSelect._ - val writePort = rAluOut.litValue.toInt - c.io.control.writeEnable.poke(true) - c.io.control.writeSelect.poke(rAluOut) - c.io.in.writeAddr.poke(5) - c.io.in.writeData(writePort).poke(0xcdef) - c.io.in.rs(0).poke(5) - c.clock.step(1) - - c.io.control.writeEnable.poke(false) - c.io.in.writeData(writePort).poke(0x1234) - c.clock.step(1) - - c.io.out.src(0).expect(0xcdef) - } - } - } -} diff --git a/npc/csrc/Flow/main.cpp b/npc/csrc/Flow/main.cpp deleted file mode 100644 index c708610..0000000 --- a/npc/csrc/Flow/main.cpp +++ /dev/null @@ -1,43 +0,0 @@ -#include -#include -#include -#include -#include -#include -#define MAX_SIM_TIME 100 -#define VERILATOR_TRACE - -int main(int argc, char **argv, char **env) { - int sim_time = 0; - Verilated::commandArgs(argc, argv); - - VFlow *top = new VFlow; - - Verilated::traceEverOn(true); - VerilatedVcdC *m_trace = new VerilatedVcdC; -#ifdef VERILATOR_TRACE - top->trace(m_trace, 5); - m_trace->open("waveform.vcd"); -#endif - for (sim_time = 0; sim_time < 10; sim_time++) { - top->eval(); - top->clock = !top->clock; - top->reset = 1; -#ifdef VERILATOR_TRACE - m_trace->dump(sim_time); -#endif - } - top->reset = 0; - for (sim_time = 10; sim_time < MAX_SIM_TIME; sim_time++) { - top->eval(); - top->clock = !top->clock; -#ifdef VERILATOR_TRACE - m_trace->dump(sim_time); -#endif - } -#ifdef VERILATOR_TRACE - m_trace->close(); -#endif - delete top; - exit(EXIT_SUCCESS); -} diff --git a/npc/csrc_nvboard/Flow/main.cpp b/npc/csrc_nvboard/Flow/main.cpp deleted file mode 100644 index 0a41d9f..0000000 --- a/npc/csrc_nvboard/Flow/main.cpp +++ /dev/null @@ -1,12 +0,0 @@ -#include -#include -// #include -#include - -const int MAX_SIM_TIME=100; - -// void nvboard_bind_all_pins(VFLow* top); - -int main(int argc, char **argv, char **env) { - return 0; -} \ No newline at end of file diff --git a/npc/flake.lock b/npc/flake.lock index 76de6c7..8763898 100644 --- a/npc/flake.lock +++ b/npc/flake.lock @@ -5,11 +5,11 @@ "systems": "systems" }, "locked": { - "lastModified": 1710146030, - "narHash": "sha256-SZ5L6eA7HJ/nmkzGG7/ISclqe6oZdOZTNoesiInkXPQ=", + "lastModified": 1701680307, + "narHash": "sha256-kAuep2h5ajznlPMD9rnQyffWG8EM/C73lejGofXvdM8=", "owner": "numtide", "repo": "flake-utils", - "rev": "b1d9ab70662946ef0850d488da1c9019f3a9752a", + "rev": "4022d587cbbfd70fe950c1e2083a02621806a725", "type": "github" }, "original": { @@ -20,11 +20,11 @@ }, "nixpkgs": { "locked": { - "lastModified": 1709961763, - "narHash": "sha256-6H95HGJHhEZtyYA3rIQpvamMKAGoa8Yh2rFV29QnuGw=", + "lastModified": 1704194953, + "narHash": "sha256-RtDKd8Mynhe5CFnVT8s0/0yqtWFMM9LmCzXv/YKxnq4=", "owner": "NixOS", "repo": "nixpkgs", - "rev": "3030f185ba6a4bf4f18b87f345f104e6a6961f34", + "rev": "bd645e8668ec6612439a9ee7e71f7eac4099d4f6", "type": "github" }, "original": { @@ -34,22 +34,6 @@ "type": "github" } }, - "nixpkgs-circt162": { - "locked": { - "lastModified": 1705645507, - "narHash": "sha256-tX3vipIAmNDBA8WNWG4oY4KyTfnm2YieTHO2BhG8ISA=", - "owner": "NixOS", - "repo": "nixpkgs", - "rev": "7995cae3ad60e3d6931283d650d7f43d31aaa5c7", - "type": "github" - }, - "original": { - "owner": "NixOS", - "repo": "nixpkgs", - "rev": "7995cae3ad60e3d6931283d650d7f43d31aaa5c7", - "type": "github" - } - }, "nur-xin": { "inputs": { "nixpkgs": [ @@ -57,11 +41,11 @@ ] }, "locked": { - "lastModified": 1707020873, - "narHash": "sha256-+dNltc7tjgTIyle/I/5siQ5IvPwu+R5Uf6e24CmjLNk=", + "lastModified": 1704450168, + "narHash": "sha256-zOLL35LX83Of64quCyxpyP8rTSO/tgrfHNm52tFo6VU=", "ref": "refs/heads/master", - "rev": "8142717e7154dbaadee0679f0224fe75cebb1735", - "revCount": 147, + "rev": "beda2a57d946f392d958755c7bb03ac092a20f42", + "revCount": 140, "type": "git", "url": "https://git.xinyang.life/xin/nur.git" }, @@ -74,7 +58,6 @@ "inputs": { "flake-utils": "flake-utils", "nixpkgs": "nixpkgs", - "nixpkgs-circt162": "nixpkgs-circt162", "nur-xin": "nur-xin" } }, diff --git a/npc/flake.nix b/npc/flake.nix index 15b910f..32aa36a 100644 --- a/npc/flake.nix +++ b/npc/flake.nix @@ -1,7 +1,6 @@ { inputs = { nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable"; - nixpkgs-circt162.url = "github:NixOS/nixpkgs/7995cae3ad60e3d6931283d650d7f43d31aaa5c7"; flake-utils.url = "github:numtide/flake-utils"; nur-xin = { url = "git+https://git.xinyang.life/xin/nur.git"; @@ -12,17 +11,14 @@ outputs = { self, ... }@inputs: with inputs; flake-utils.lib.eachDefaultSystem (system: let - pkgs = import nixpkgs { inherit system; config.allowUnfree = true; }// + pkgs = nixpkgs.legacyPackages.${system} // { nur.xin = nur-xin.legacyPackages.${system}; }; in { devShells.default = with pkgs; mkShell { - CHISEL_FIRTOOL_PATH = "${nixpkgs-circt162.legacyPackages.${system}.circt}/bin"; packages = [ clang-tools - # rnix-lsp - coursier - espresso + rnix-lsp gdb jre @@ -40,7 +36,7 @@ cmake sbt nur.xin.nvboard - nixpkgs-circt162.legacyPackages.${system}.circt + self.packages.${system}.circt yosys ]; buildInputs = [ diff --git a/npc/resource/addi.txt b/npc/resource/addi.txt deleted file mode 100644 index 8eb11e4..0000000 --- a/npc/resource/addi.txt +++ /dev/null @@ -1,10 +0,0 @@ -00114113 -00114113 -00114113 -00114113 -00114113 -00114113 -00114113 -00114113 -00114113 -00114113