diff --git a/nemu/Kconfig b/nemu/Kconfig index 5816143..85074bd 100644 --- a/nemu/Kconfig +++ b/nemu/Kconfig @@ -180,7 +180,7 @@ config ITRACE_BUFFER default 10 config MTRACE - depends on TRACE + depends on TRACE && TARGET_NATIVE_ELF && ENGINE_INTERPRETER bool "Enable memory tracing" default n diff --git a/nemu/src/cpu/difftest/ref.c b/nemu/src/cpu/difftest/ref.c index 3f44732..7d59b4a 100644 --- a/nemu/src/cpu/difftest/ref.c +++ b/nemu/src/cpu/difftest/ref.c @@ -25,7 +25,7 @@ __EXPORT void difftest_memcpy(paddr_t addr, void *buf, size_t n, if (direction == DIFFTEST_TO_REF) { memcpy(guest_to_host(addr), buf, n); } else { - memcpy(buf, guest_to_host(addr), n); + assert(0); } } diff --git a/npc/.gitignore b/npc/.gitignore index 5a4f7bc..e0793d8 100644 --- a/npc/.gitignore +++ b/npc/.gitignore @@ -16,4 +16,3 @@ hs_err_pid* .direnv/ compile_commands.json -*.vcd diff --git a/npc/CMakeLists.txt b/npc/CMakeLists.txt index bb6cd95..bcd356b 100644 --- a/npc/CMakeLists.txt +++ b/npc/CMakeLists.txt @@ -10,10 +10,10 @@ enable_testing() list(APPEND CMAKE_MODULE_PATH ${PROJECT_SOURCE_DIR}/cmake) # -- Build options -option(BUILD_USE_BLOOP "Whether to use bloop to speed up elaborate" OFF) +option(BUILD_USE_BLOOP "Whether to use bloop to speed up elaborate" ON) option(BUILD_SIM_TARGET "Whether to build verilator simulation binary" ON) cmake_dependent_option(BUILD_SIM_NVBOARD_TARGET "Whether to build nvboard target" OFF "BUILD_SIM_TARGET" OFF) -option(ENABLE_YSYX_GIT_TRACKER "Ysyx tracker support" ON) +option(ENABLE_YSYX_GIT_TRACKER "Ysyx tracker support" OFF) set(TOPMODULE "Flow" CACHE STRING "Topmodule name in chisel") set(DIFFTEST_LIB "" CACHE STRING "Dynamic library file used as difftest reference") @@ -34,6 +34,8 @@ if(BUILD_SIM_NVBOARD_TARGET) find_package(SDL2_image REQUIRED) endif() find_package(CLI11 CONFIG REQUIRED) +# TODO: Not required +find_package(LLVM CONFIG REQUIRED) option(ENABLE_SDB "Enable simple debugger" ON) @@ -45,11 +47,14 @@ find_path(NVBOARD_INCLUDE_DIR NAMES nvboard.h) set(SCALA_CORE "${CMAKE_CURRENT_SOURCE_DIR}/core") set(CHISEL_MODULE_CLASS "${CMAKE_PROJECT_NAME}.${TOPMODULE}") +# Verilog files are generted in CHISEL_OUTPUT_TMP_DIR and copy to +# CHISEL_OUTPUT_DIR if content changes set(CHISEL_OUTPUT_DIR ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc) +set(CHISEL_OUTPUT_TMP_DIR ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc_tmp) set(CHISEL_OUTPUT_VERILATOR_CONF ${CHISEL_OUTPUT_DIR}/conf.vlt) set(CHISEL_OUTPUT_TOPMODULE ${CHISEL_OUTPUT_DIR}/${TOPMODULE}.sv) -set(CHISEL_EMIT_ARGS "--target-dir ${CHISEL_OUTPUT_DIR}") +set(CHISEL_EMIT_ARGS "--target-dir ${CHISEL_OUTPUT_TMP_DIR}") # -- Build NVBoard executable if(BUILD_SIM_NVBOARD_TARGET) @@ -64,9 +69,15 @@ add_subdirectory(csrc) # -- Add build tracking if(ENABLE_YSYX_GIT_TRACKER) - add_custom_target( - ysyx_git_tracer ALL - COMMAND ${CMAKE_SOURCE_DIR}/../git_commit.sh "build_${CMAKE_PROJECT_NAME}_V${TOPMODULE}" - WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/.. + add_custom_command( + TARGET V${TOPMODULE}_nvboard PRE_BUILD + COMMAND ${CMAKE_SOURCE_DIR}/../git_commit.sh "build_${CMAKE_PROJECT_NAME}_V${TOPMODULE}_nvboard" + WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/.. + ) + + add_custom_command( + TARGET V${TOPMODULE} PRE_BUILD + COMMAND ${CMAKE_SOURCE_DIR}/../git_commit.sh "build_${CMAKE_PROJECT_NAME}_V${TOPMODULE}" + WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/.. ) endif() diff --git a/npc/LICENSE b/npc/LICENSE deleted file mode 100644 index f288702..0000000 --- a/npc/LICENSE +++ /dev/null @@ -1,674 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 3, 29 June 2007 - - Copyright (C) 2007 Free Software Foundation, Inc. - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The GNU General Public License is a free, copyleft license for -software and other kinds of works. - - The licenses for most software and other practical works are designed -to take away your freedom to share and change the works. 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If not, see . - -Also add information on how to contact you by electronic and paper mail. - - If the program does terminal interaction, make it output a short -notice like this when it starts in an interactive mode: - - Copyright (C) - This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. - This is free software, and you are welcome to redistribute it - under certain conditions; type `show c' for details. - -The hypothetical commands `show w' and `show c' should show the appropriate -parts of the General Public License. Of course, your program's commands -might be different; for a GUI interface, you would use an "about box". - - You should also get your employer (if you work as a programmer) or school, -if any, to sign a "copyright disclaimer" for the program, if necessary. -For more information on this, and how to apply and follow the GNU GPL, see -. - - The GNU General Public License does not permit incorporating your program -into proprietary programs. If your program is a subroutine library, you -may consider it more useful to permit linking proprietary applications with -the library. If this is what you want to do, use the GNU Lesser General -Public License instead of this License. But first, please read -. diff --git a/npc/cmake/ChiselBuild.cmake b/npc/cmake/ChiselBuild.cmake index 789b476..aa830f7 100644 --- a/npc/cmake/ChiselBuild.cmake +++ b/npc/cmake/ChiselBuild.cmake @@ -3,7 +3,6 @@ # NOTE: Must reconfigure if we add new files in SCALA_CORE directory file(GLOB_RECURSE SCALA_CORE_SOURCES "${SCALA_CORE}/src/main/scala/*.scala") file(GLOB_RECURSE SCALA_CORE_RESOURCES "${SCALA_CORE}/src/main/resources/*") -message(STATUS "Found scala source file: ${SCALA_CORE_SOURCES}") set(CHISEL_DEPENDENCY ${SCALA_CORE_SOURCES} ${SCALA_CORE_RESOURCES} ${SCALA_CORE}/build.sbt) if(BUILD_USE_BLOOP) @@ -19,8 +18,9 @@ if(BUILD_USE_BLOOP) string(REPLACE " " ";" CHISEL_EMIT_ARGS_LIST ${CHISEL_EMIT_ARGS}) list(TRANSFORM CHISEL_EMIT_ARGS_LIST PREPEND "--args;") add_custom_command( - OUTPUT ${CHISEL_OUTPUT_TOPMODULE} ${CHISEL_OUTPUT_VERILATOR_CONF} - COMMAND bloop run --no-color root ${CHISEL_EMIT_ARGS_LIST} + OUTPUT ${CHISEL_OUTPUT_TOPMODULE} + COMMAND bloop run root ${CHISEL_EMIT_ARGS_LIST} + COMMAND ${CMAKE_COMMAND} -E copy_directory_if_different ${CHISEL_OUTPUT_TMP_DIR} ${CHISEL_OUTPUT_DIR} WORKING_DIRECTORY ${SCALA_CORE} DEPENDS ${CHISEL_DEPENDENCY} COMMAND_EXPAND_LISTS @@ -35,10 +35,11 @@ else() set(CHISEL_TARGET sbt_${TOPMODULE}) set(CHISEL_TEST_TARGET sbt_${TOPMODULE}_test) add_custom_command( - OUTPUT ${CHISEL_OUTPUT_TOPMODULE} ${CHISEL_OUTPUT_VERILATOR_CONF} + OUTPUT ${CHISEL_OUTPUT_TOPMODULE} COMMAND sbt "run ${CHISEL_EMIT_ARGS}" + COMMAND ${CMAKE_COMMAND} -E copy_directory_if_different ${CHISEL_OUTPUT_TMP_DIR} ${CHISEL_OUTPUT_DIR} WORKING_DIRECTORY ${SCALA_CORE} - DEPENDS ${CHISEL_DEPENDENCY} + # DEPENDS ${CHISEL_DEPENDENCY} test.scala VERBATIM COMMENT "Run sbt from CMake" ) @@ -49,10 +50,13 @@ else() ) endif() -if(NOT EXISTS ${CHISEL_OUTPUT_TOPMODULE}) +if(NOT EXISTS ${CHISEL_OUTPUT_DIR}) # Probably cold build, generate verilog at configure time to produce top module file execute_process( COMMAND sbt "run ${CHISEL_EMIT_ARGS}" WORKING_DIRECTORY ${SCALA_CORE} ) + execute_process( + COMMAND ${CMAKE_COMMAND} -E copy_directory ${CHISEL_OUTPUT_TMP_DIR} ${CHISEL_OUTPUT_DIR} + ) endif() diff --git a/npc/core/project/build.properties b/npc/core/project/build.properties deleted file mode 100644 index 04267b1..0000000 --- a/npc/core/project/build.properties +++ /dev/null @@ -1 +0,0 @@ -sbt.version=1.9.9 diff --git a/npc/core/project/plugin.sbt b/npc/core/project/plugin.sbt deleted file mode 100644 index 0c0f704..0000000 --- a/npc/core/project/plugin.sbt +++ /dev/null @@ -1 +0,0 @@ -addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.2") diff --git a/npc/core/src/main/resources/RamDpi.v b/npc/core/src/main/resources/RamDpi.v index 0f4308b..c9f8b7c 100644 --- a/npc/core/src/main/resources/RamDpi.v +++ b/npc/core/src/main/resources/RamDpi.v @@ -2,8 +2,6 @@ import "DPI-C" function int pmem_read(input int addr); import "DPI-C" function void pmem_write(input int waddr, input int wdata, input byte wmask); module RamDpi ( - input clock, - input reset, input writeEnable, input valid, input [31:0] writeAddr, diff --git a/npc/core/src/main/scala/components/ALU.scala b/npc/core/src/main/scala/components/ALU.scala index 44e9c14..0c22b15 100644 --- a/npc/core/src/main/scala/components/ALU.scala +++ b/npc/core/src/main/scala/components/ALU.scala @@ -6,13 +6,13 @@ import shapeless.{HNil, ::} class ALUControlInterface extends Bundle { object OpSelect extends ChiselEnum { - val aOpAdd, aOpSub, aOpNot, aOpAnd, aOpOr, aOpXor, aOpSlt, aOpSltu, aOpSll, aOpSrl, aOpSra = Value + val aOpAdd, aOpSub, aOpNot, aOpAnd, aOpOr, aOpXor, aOpSlt, aOpSll, aOpSrl, aOpSra = Value } object SrcASelect extends ChiselEnum { val aSrcARs1, aSrcAPc, aSrcAZero = Value } object SrcBSelect extends ChiselEnum { - val aSrcBRs2, aSrcBImmI, aSrcBImmJ, aSrcBImmS, aSrcBImmU = Value + val aSrcBRs2, aSrcBImmI, aSrcBImmJ, aSrcBImmB, aSrcBImmS = Value } val op = Input(OpSelect()) val srcASelect = Input(SrcASelect()) @@ -45,8 +45,7 @@ class ALU[T <: UInt](tpe: T) extends Module { val not = ~a val or = a | b val xor = a ^ b - val slt = a.asSInt < b.asSInt - val sltu = a < b + val slt = a < b val sll = a << b(log2Ceil(tpe.getWidth), 0) val srl = a >> b(log2Ceil(tpe.getWidth), 0) val sra = a.asSInt >> b(log2Ceil(tpe.getWidth), 0) @@ -62,7 +61,6 @@ class ALU[T <: UInt](tpe: T) extends Module { aOpOr -> or, aOpXor -> xor, aOpSlt -> slt, - aOpSltu -> sltu, aOpSll -> sll, aOpSrl -> srl, aOpSra -> sra.asUInt diff --git a/npc/core/src/main/scala/components/Mem.scala b/npc/core/src/main/scala/components/Mem.scala index 24f9927..7562730 100644 --- a/npc/core/src/main/scala/components/Mem.scala +++ b/npc/core/src/main/scala/components/Mem.scala @@ -23,8 +23,6 @@ class RamControlInterface(addrWidth: Int) extends Bundle { * We need a way to merge two bundles together */ class RamInterface[T <: Data](tpe: T, addrWidth: Int) extends RamControlInterface(addrWidth) { - val clock = Input(Clock()) - val reset = Input(Reset()) val writeAddr = Input(UInt(addrWidth.W)) val writeData = Input(tpe) val readAddr = Input(UInt(addrWidth.W)) diff --git a/npc/core/src/main/scala/top/FlowMain.scala b/npc/core/src/main/scala/top/FlowMain.scala index b6aa888..899783c 100644 --- a/npc/core/src/main/scala/top/FlowMain.scala +++ b/npc/core/src/main/scala/top/FlowMain.scala @@ -130,16 +130,6 @@ class Control(width: Int) extends RawModule { // Exe | op :: srcASelect :: srcBSelect :: signExt :: HNil // Mem | valid :: writeMask :: writeEnable :: HNil - (lui , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc):: - r(aOpAdd) :: r(aSrcAZero) :: r(aSrcBImmU) :: r(false.B) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), - - (auipc , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc):: - r(aOpAdd) :: r(aSrcAPc) :: r(aSrcBImmU) :: r(false.B) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), - // ---- Control Transfer Instructions ---- (jal , (r(true.B) :: r(rNpc) :: r(false.B) :: r(pExeOut) :: @@ -148,37 +138,37 @@ class Control(width: Int) extends RawModule { (jalr , (r(true.B) :: r(rNpc) :: r(false.B) :: r(pExeOut) :: - r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: r(false.B) :: + r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmJ) :: r(false.B) :: r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), (beq , (r(false.B) :: l(WriteSelect) :: - r(true.B) :: r(pStaticNpc) :: - r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: + r(true.B) :: r(pExeOut) :: + r(aOpSlt) :: r(aSrcAPc) :: r(aSrcBImmB) :: l(Bool()) :: r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), (bne , (r(false.B) :: l(WriteSelect) :: - r(true.B) :: r(pStaticNpc) :: - r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: + r(true.B) :: r(pExeOut) :: + r(aOpSlt) :: r(aSrcAPc) :: r(aSrcBImmB) :: l(Bool()) :: r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), (blt , (r(false.B) :: l(WriteSelect) :: - r(true.B) :: r(pStaticNpc) :: - r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(true.B) :: + r(true.B) :: r(pExeOut) :: + r(aOpSlt) :: r(aSrcAPc) :: r(aSrcBImmB) :: r(true.B) :: r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), (bge , (r(false.B) :: l(WriteSelect) :: - r(true.B) :: r(pStaticNpc) :: - r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(true.B) :: + r(true.B) :: r(pExeOut) :: + r(aOpSlt) :: r(aSrcAPc) :: r(aSrcBImmB) :: r(true.B) :: r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), (bltu , (r(false.B) :: l(WriteSelect):: - r(true.B) :: r(pStaticNpc) :: - r(aOpSltu) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(false.B) :: + r(true.B) :: r(pExeOut) :: + r(aOpSlt) :: r(aSrcAPc) :: r(aSrcBImmB) :: r(false.B) :: r(false.B) :: l(UInt(4.W)) :: r(false.B) :: HNil)), (bgeu , (r(false.B) :: l(WriteSelect):: - r(true.B) :: r(pStaticNpc) :: - r(aOpSltu) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(false.B) :: + r(true.B) :: r(pExeOut) :: + r(aOpSlt) :: r(aSrcAPc) :: r(aSrcBImmB) :: r(false.B) :: r(false.B) :: l(UInt(4.W)) :: r(false.B) :: HNil)), // ---- Memory Access Instructions ---- @@ -186,49 +176,39 @@ class Control(width: Int) extends RawModule { (lb , (r(true.B) :: r(rMemOut) :: r(false.B) :: r(pStaticNpc) :: r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(true.B) :: r(1.U(4.W)) :: r(false.B) :: HNil)), + r(true.B) :: l(UInt(4.W)) :: r(false.B) :: HNil)), - (lbu , (r(true.B) :: r(rMemOut) :: + (lh , (r(true.B) :: r(rMemOut) :: r(false.B) :: r(pStaticNpc) :: r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(true.B) :: r(0.U(4.W)) :: r(false.B) :: HNil)), - - (lh , (r(true.B) :: r(rMemOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(true.B) :: r(3.U(4.W)) :: r(false.B) :: HNil)), - - (lhu , (r(true.B) :: r(rMemOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(true.B) :: r(2.U(4.W)) :: r(false.B) :: HNil)), + r(true.B) :: l(UInt(4.W)) :: r(false.B) :: HNil)), (lw , (r(true.B) :: r(rMemOut) :: r(false.B) :: r(pStaticNpc) :: r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(true.B) :: r(14.U(4.W)) :: r(false.B) :: HNil)), + r(true.B) :: l(UInt(4.W)) :: r(false.B) :: HNil)), (sb , (r(false.B) :: l(WriteSelect):: r(false.B) :: r(pStaticNpc) :: - r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmS) :: l(Bool()) :: - r(true.B) :: r(1.U(4.W)) :: r(true.B) :: HNil)), + r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: + r(true.B) :: r(1.U(4.W)) :: r(false.B) :: HNil)), (sh , (r(false.B) :: l(WriteSelect):: r(false.B) :: r(pStaticNpc) :: - r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmS) :: l(Bool()) :: - r(true.B) :: r(3.U(4.W)) :: r(true.B) :: HNil)), + r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: + r(true.B) :: r(3.U(4.W)) :: r(false.B) :: HNil)), (sw , (r(false.B) :: l(WriteSelect):: r(false.B) :: r(pStaticNpc) :: - r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmS) :: l(Bool()) :: - r(true.B) :: r(15.U(4.W)) :: r(true.B) :: HNil)), + r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: + r(true.B) :: r(15.U(4.W)) :: r(false.B) :: HNil)), // ---- Integer Computational Instructions --- (addi , (r(true.B) :: r(rAluOut) :: r(false.B) :: r(pStaticNpc) :: r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), (slti , (r(true.B) :: r(rAluOut) :: r(false.B) :: r(pStaticNpc) :: @@ -237,7 +217,7 @@ class Control(width: Int) extends RawModule { (sltiu , (r(true.B) :: r(rAluOut) :: r(false.B) :: r(pStaticNpc) :: - r(aOpSltu) :: r(aSrcARs1) :: r(aSrcBImmI) :: r(false.B) :: + r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBImmI) :: r(false.B) :: r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), (xori , (r(true.B) :: r(rAluOut) :: @@ -292,7 +272,7 @@ class Control(width: Int) extends RawModule { (sltu , (r(true.B) :: r(rAluOut) :: r(false.B) :: r(pStaticNpc) :: - r(aOpSltu) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(false.B) :: + r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(false.B) :: r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), (xor , (r(true.B) :: r(rAluOut) :: @@ -338,6 +318,8 @@ class Control(width: Int) extends RawModule { .foreach({ case (src, dst) => dst.toOption.get := src.asTypeOf(dst.toOption.get) }) + + pc.useImmB := DontCare } import flow.components.{RegisterFile, ProgramCounter, ALU, RamDpi} @@ -363,59 +345,37 @@ class Flow extends Module { val npc = Wire(dataType) npc := pc.out + 4.U pc.in.exeOut := alu.out.result - pc.in.immB := Cat(Fill(20, inst(31)), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)) + pc.in.immB := Cat(Fill(20, inst(31)), inst(7), inst(30, 25), inst(11, 8), inst(0)) control.inst := inst reg.control <> control.reg // FIXME: Probably optimizable with bulk connection pc.control <> control.pc - pc.control.useImmB := control.pc.useImmB alu.control <> control.alu val branchUseSlt = Wire(Bool()) val branchInvertResult = Wire(Bool()) branchUseSlt := inst(14) branchInvertResult := inst(12) val _branchResult = Mux(branchUseSlt, alu.out.result(0), alu.out.eq) - val branchResult = Mux(branchInvertResult, !_branchResult, _branchResult) - pc.control.useImmB := control.pc.useImmB && branchResult - // printf(cf"_branchResult = ${_branchResult}, branchResult = ${branchResult}\n") - // printf(cf"pcin.useImmB = ${pc.control.useImmB}, control.out.useImmB = ${control.pc.useImmB} \n") + val branchResult = Mux(branchInvertResult, _branchResult, !_branchResult) + pc.control.useImmB := control.pc.useImmB && _branchResult import control.reg.WriteSelect._ reg.in.writeData(lit(rAluOut)) := alu.out.result - val maskedData = ram.io.readData & Cat( - Fill(8, ram.io.writeMask(3)), - Fill(8, ram.io.writeMask(2)), - Fill(8, ram.io.writeMask(1)), - "b11111111".U) - - val doSignExt = control.ram.writeMask(0) - val signExt16 = control.ram.writeMask(1) - when(!doSignExt) { - reg.in.writeData(lit(rMemOut)) := maskedData - // printf(cf"!doSignExt\n") - }.elsewhen(signExt16) { - reg.in.writeData(lit(rMemOut)) := Cat(Fill(16, maskedData(15)), maskedData(15, 0)) - // printf(cf"elsewhen\n") - }.otherwise { - reg.in.writeData(lit(rMemOut)) := Cat(Fill(24, maskedData(7)), maskedData(7, 0)) - // printf(cf"otherwise\n") - } - // printf(cf"maskedData = ${maskedData}, writeData = ${reg.in.writeData(lit(rMemOut))}\n") + // TODO: Read address in load command goes here + reg.in.writeData(lit(rMemOut)) := ram.io.readData reg.in.writeData(lit(rNpc)) := npc reg.in.writeAddr := inst(11, 7) reg.in.rs(0) := inst(19, 15) // rs1 reg.in.rs(1) := inst(24, 20) // rs2 - // TODO: Bulk connection here - ram.io.clock := clock - ram.io.reset := reset + // TODO: Memory write goes here ram.io.writeAddr := alu.out.result ram.io.writeData := reg.out.src(1) ram.io.writeMask := control.ram.writeMask ram.io.writeEnable := control.ram.writeEnable - ram.io.valid := control.ram.valid + ram.io.valid := true.B ram.io.readAddr := alu.out.result import control.alu.SrcASelect._ @@ -425,12 +385,11 @@ class Flow extends Module { alu.in.a(lit(aSrcAZero)) := 0.U alu.in.b(lit(aSrcBRs2)) := reg.out.src(1) - // alu.in.b(lit(aSrcBImmI)) := inst(31, 20).pad(aSrcBImmI.getWidth) - alu.in.b(lit(aSrcBImmI)) := Cat(Fill(20, inst(31)), inst(31, 20)) + alu.in.b(lit(aSrcBImmI)) := inst(31, 20).pad(aSrcBImmI.getWidth) alu.in.b(lit(aSrcBImmJ)) := Cat(Fill(12, inst(31)), inst(19, 12), inst(20), inst(30, 25), inst(24, 21), 0.U(1.W)) - alu.in.b(lit(aSrcBImmS)) := Cat(Fill(20, inst(31)), inst(31), inst(30, 25), inst(11, 8), inst(7)) - alu.in.b(lit(aSrcBImmU)) := Cat(inst(31, 12), 0.U(12.W)) + alu.in.b(lit(aSrcBImmB)) := Cat(Fill(20, inst(31)), inst(7), inst(30, 25), inst(11, 8), inst(0)) + alu.in.b(lit(aSrcBImmS)) := Cat(inst(31), inst(19, 12), inst(20), inst(30, 25), inst(24, 21), 0.U(1.W)).pad(aSrcBImmS.getWidth) - Trace.traceName(pc.out) + Trace.traceName(pc.out); dontTouch(control.out) } diff --git a/npc/csrc/Flow/CMakeLists.txt b/npc/csrc/Flow/CMakeLists.txt index 16aaef1..ad8d2e9 100644 --- a/npc/csrc/Flow/CMakeLists.txt +++ b/npc/csrc/Flow/CMakeLists.txt @@ -1,8 +1,8 @@ include(ChiselBuild) add_executable(V${TOPMODULE} config.cpp main.cpp) -target_link_libraries(V${TOPMODULE} PRIVATE sdb) +target_link_libraries(V${TOPMODULE} PRIVATE disasm sdb) -verilate(V${TOPMODULE} TRACE THREADS +verilate(V${TOPMODULE} TRACE COVERAGE THREADS TOP_MODULE ${TOPMODULE} PREFIX V${TOPMODULE} SOURCES ${CHISEL_OUTPUT_TOPMODULE} ${CHISEL_OUTPUT_VERILATOR_CONF} diff --git a/npc/csrc/Flow/config.cpp b/npc/csrc/Flow/config.cpp index fd49141..4d8338b 100644 --- a/npc/csrc/Flow/config.cpp +++ b/npc/csrc/Flow/config.cpp @@ -7,16 +7,18 @@ void Config::cli_parse(int argc, char **argv) { ->check(CLI::ExistingFile); app.add_flag("!--no-bin", memory_file_binary, "Memory file is in text format"); - app.add_option("--wav", wavefile, "output .vcd file path"); + app.add_flag("--trace", do_trace, "Enable tracing"); + app.add_option("--wav", wavefile, "output .vcd file path") + ->check([=](const std::string &) { + if (!do_trace) + throw CLI::ValidationError( + "dependency", "You must turn on trace before specify wave file"); + return std::string(); + }); app.add_option("-t", max_sim_time, "Max simulation timestep"); app.add_option("--diff-lib", lib_ref, "Dynamic library file of difftest reference") ->check(CLI::ExistingFile); - app.add_flag("--mtrace", do_mtrace, "Enable memory tracing"); - app.add_option( - "--mtrace-range", mtrace_ranges, - "Specify memory tracing range (default: 0x80000000-0x8fffffff)") - ->delimiter(','); try { app.parse(argc, argv); diff --git a/npc/csrc/Flow/config.hpp b/npc/csrc/Flow/config.hpp new file mode 100644 index 0000000..9f5873c --- /dev/null +++ b/npc/csrc/Flow/config.hpp @@ -0,0 +1,20 @@ +#ifndef _NPC_CONFIG_H_ +#define _NPC_CONFIG_H_ +#include +#include +#include +#include + +struct Config { + std::filesystem::path memory_file; + uint64_t max_sim_time = 1000; + bool memory_file_binary = {true}; + bool do_trace{false}; + std::filesystem::path wavefile; + std::filesystem::path lib_ref; + void cli_parse(int argc, char **argv); +}; + +extern Config config; + +#endif \ No newline at end of file diff --git a/npc/csrc/Flow/main.cpp b/npc/csrc/Flow/main.cpp index 664db56..b1c37c9 100644 --- a/npc/csrc/Flow/main.cpp +++ b/npc/csrc/Flow/main.cpp @@ -1,35 +1,23 @@ #include "VFlow___024root.h" +#include "config.hpp" +#include "disasm.hpp" +#include "vl_wrapper.hpp" +#include "vpi_user.h" +#include "vpi_wrapper.hpp" #include -#include #include #include -#include -#include -#include +#include #include -#include -#include #include -#include -#include -#include using VlModule = VlModuleInterfaceCommon; using Registers = _RegistersVPI; -// SDB::SDB sdb_dut; -using CPUState = CPUStateBase; -bool g_skip_memcheck = false; -CPUState npc_cpu; -VlModule *top; -Registers *regs; -vpiHandle pc = nullptr; - extern "C" { void *pmem_get() { - static auto pmem = - new Memory(config.memory_file, config.memory_file_binary, - std::move(config.mtrace_ranges)); + static auto pmem = new Memory(config.memory_file, + config.memory_file_binary); return pmem; } @@ -38,33 +26,26 @@ int pmem_read(int raddr) { auto mem = static_cast *>(pmem); // TODO: Do memory difftest at memory read and write to diagnose at a finer // granularity - if (config.do_mtrace) - mem->trace(raddr, true, regs->get_pc()); return mem->read(raddr); } void pmem_write(int waddr, int wdata, char wmask) { void *pmem = pmem_get(); auto mem = static_cast *>(pmem); - if (config.do_mtrace) - mem->trace((std::size_t)waddr, false, regs->get_pc(), wdata); return mem->write((std::size_t)waddr, wdata, wmask); } } -namespace NPC { -void npc_memcpy(paddr_t addr, void *buf, size_t sz, bool direction) { - if (direction == TRM_FROM_MACHINE) { - memcpy( - buf, - static_cast *>(pmem_get())->guest_to_host(addr), - sz); - } -}; +Disassembler d{"riscv32-pc-linux-gnu"}; -void npc_regcpy(void *p, bool direction) { +VlModule *top; +Registers *regs; +vpiHandle pc = nullptr; +void difftest_memcpy(paddr_t, void *, size_t, bool){}; - if (direction == TRM_FROM_MACHINE) { +void difftest_regcpy(void *p, bool direction) { + + if (direction == DIFFTEST_FROM_REF) { ((CPUState *)p)->pc = regs->get_pc(); for (int i = 0; i < 32; i++) { ((CPUState *)p)->reg[i] = (*regs)[i]; @@ -72,7 +53,7 @@ void npc_regcpy(void *p, bool direction) { } } -void npc_exec(uint64_t n) { +void difftest_exec(uint64_t n) { while (n--) { for (int i = 0; i < 2; i++) { if (top->is_posedge()) { @@ -83,61 +64,43 @@ void npc_exec(uint64_t n) { } } } +// std::cout << d.disassemble(top->rootp->Flow__DOT__pc__DOT__pc_reg, (uint8_t *)&top->rootp->Flow__DOT___ram_inst, 4) << std::endl; -void npc_atexit(void) { - delete top; - delete regs; -} - -void npc_init(int port) { - top = new VlModule{config.wavefile}; +void difftest_init(int port) { + // top = std::make_unique(config.do_trace, config.wavefile); + top = new VlModule{config.do_trace, config.wavefile}; regs = new Registers("TOP.Flow.reg_0.regFile_", "TOP.Flow.pc.out"); - atexit(npc_atexit); top->reset_eval(10); } -class DutTrmInterface : public TrmInterface { -public: - DutTrmInterface(memcpy_t f_memcpy, regcpy_t f_regcpy, exec_t f_exec, - init_t f_init, void *cpu_state) - : TrmInterface{f_memcpy, f_regcpy, f_exec, f_init, cpu_state} {} - word_t at(std::string name) const override { - return ((CPUState *)cpu_state)->at(name); - } - - word_t at(paddr_t addr) const override { - word_t buf; - this->memcpy(addr, &buf, sizeof(word_t), TRM_FROM_MACHINE); - return buf; - } - void print(std::ostream &os) const override {} -}; - -DutTrmInterface npc_interface = - DutTrmInterface{&npc_memcpy, &npc_regcpy, &npc_exec, &npc_init, &npc_cpu}; -}; // namespace NPC +DifftestInterface dut_interface = DifftestInterface{ + &difftest_memcpy, &difftest_regcpy, &difftest_exec, &difftest_init}; +SDB::SDB sdb_dut; extern "C" { word_t reg_str2val(const char *name, bool *success) { - return npc_cpu.reg_str2val(name, success); + return sdb_dut.reg_str2val(name, success); } } int main(int argc, char **argv, char **env) { config.cli_parse(argc, argv); - if (config.max_sim_time > 1) { - NPC::npc_interface.exec(config.max_sim_time / 2); - } else { - /* -- Difftest -- */ - std::filesystem::path ref{config.lib_ref}; - RefTrmInterface ref_interface{ref}; - DifftestTrmInterface diff_interface{NPC::npc_interface, ref_interface, - pmem_get(), 128 * 1024}; - SDB::SDB sdb_diff{diff_interface}; + /* -- Difftest -- */ + std::filesystem::path ref{config.lib_ref}; + DifftestInterface ref_interface = DifftestInterface{ref}; - int t = 8; - sdb_diff.main_loop(); + Difftest> diff{dut_interface, ref_interface, + pmem_get(), 128}; + int t = 8; + sdb_dut.main_loop(); + while (t--) { + if (!diff.step(1)) { + uint32_t pc = regs->get_pc(); + uint32_t inst = pmem_read(pc); + std::cout << diff << d.disassemble(pc, (uint8_t *)&inst, 4) << std::endl; + return EXIT_FAILURE; + } } return 0; diff --git a/npc/csrc/Flow/vl_wrapper.hpp b/npc/csrc/Flow/vl_wrapper.hpp new file mode 100644 index 0000000..4d42b55 --- /dev/null +++ b/npc/csrc/Flow/vl_wrapper.hpp @@ -0,0 +1,65 @@ +#ifndef _NPC_TRACER_H_ +#define _NPC_TRACER_H_ +#include +#include + +template class Tracer { + std::shared_ptr top; + std::unique_ptr m_trace; + uint64_t cycle = 0; + +public: + Tracer(T *top, std::filesystem::path wavefile) { + top = top; + Verilated::traceEverOn(true); + m_trace = std::make_unique(); + top->trace(m_trace.get(), 5); + m_trace->open(wavefile.c_str()); + } + ~Tracer() { m_trace->close(); } + + /** + * Dump signals to waveform file. Must be called once after every top->eval() + * call. + */ + void update() { m_trace->dump(cycle++); } +}; + +template class VlModuleInterfaceCommon : public T { + uint64_t sim_time = 0; + uint64_t posedge_cnt = 0; + std::unique_ptr> tracer; + +public: + VlModuleInterfaceCommon(bool do_trace, + std::filesystem::path wavefile = "waveform.vcd") { + if (do_trace) + tracer = std::make_unique>(this, wavefile); + } + void eval() { + if (this->is_posedge()) { + posedge_cnt++; + } + T::clock = !T::clock; + sim_time++; + T::eval(); + if (tracer) + tracer->update(); + } + void eval(int n) { + for (int i = 0; i < n; i++) { + this->eval(); + } + } + void reset_eval(int n) { + this->reset = 1; + this->eval(n); + this->reset = 0; + } + bool is_posedge() { + // Will be posedge when eval is called + return T::clock == 0; + } +}; + +#endif diff --git a/npc/include/vpi_wrapper.hpp b/npc/csrc/Flow/vpi_wrapper.hpp similarity index 100% rename from npc/include/vpi_wrapper.hpp rename to npc/csrc/Flow/vpi_wrapper.hpp diff --git a/npc/include/components.hpp b/npc/include/components.hpp index 91847a7..fced1af 100644 --- a/npc/include/components.hpp +++ b/npc/include/components.hpp @@ -1,20 +1,23 @@ #ifndef _NPC_COMPONENTS_H_ #define _NPC_COMPONENTS_H_ -#include "types.h" #include -#include -#include #include #include #include #include #include #include -#include #include #include -#include + +const std::map riscv32_regs_by_name{ + {"$0", 0}, {"ra", 1}, {"sp", 2}, {"gp", 3}, {"tp", 4}, {"t0", 5}, + {"t1", 6}, {"t2", 7}, {"s0", 8}, {"s1", 9}, {"a0", 10}, {"a1", 11}, + {"a2", 12}, {"a3", 13}, {"a4", 14}, {"a5", 15}, {"a6", 16}, {"a7", 17}, + {"s2", 18}, {"s3", 19}, {"s4", 20}, {"s5", 21}, {"s6", 22}, {"s7", 23}, + {"s8", 24}, {"s9", 25}, {"s10", 26}, {"s11", 27}, {"t3", 28}, {"t4", 29}, + {"t5", 30}, {"t6", 31}}; template class _RegistersBase { std::array regs; @@ -33,6 +36,13 @@ public: }; template class Memory { + std::size_t addr_to_index(std::size_t addr) { + if (addr < 0x80000000) { + return 0; + } + // Linear mapping + return (addr >> 2) - 0x20000000; + } uint32_t expand_bits(uint8_t bits) { uint32_t x = bits; x = (x | (x << 7) | (x << 14) | (x << 21)) & 0x01010101; @@ -43,10 +53,7 @@ template class Memory { public: std::array mem; - std::vector> trace_ranges; - Memory(std::filesystem::path filepath, bool is_binary, - std::vector> &&trace_ranges) - : trace_ranges(std::move(trace_ranges)) { + Memory(std::filesystem::path filepath, bool is_binary = true) { if (!std::filesystem::exists(filepath)) throw std::runtime_error("Memory file not found"); if (is_binary) { @@ -66,9 +73,9 @@ public: /** * Always reads and returns 4 bytes from the address raddr & ~0x3u. */ - T read(paddr_t raddr) { + T read(int raddr) { // printf("raddr: 0x%x\n", raddr); - return *(word_t *)guest_to_host(raddr); + return mem[addr_to_index((uint32_t)raddr)]; } /** * Always writes to the 4 bytes at the address `waddr` & ~0x3u. @@ -76,44 +83,9 @@ public: * For example, wmask = 0x3 means only the lowest 2 bytes are written, * and the other bytes in memory remain unchanged. */ - void write(paddr_t waddr, T wdata, char wmask) { + void write(int waddr, T wdata, char wmask) { // printf("waddr: 0x%x\n", waddr); - uint8_t *p_data = (uint8_t *)&wdata; - while (wmask & 0x1) { - memcpy(guest_to_host(waddr), p_data, 1); - waddr++; - p_data++; - wmask >>= 1; - } - } - void *guest_to_host(std::size_t addr) { - extern bool g_skip_memcheck; - if (g_skip_memcheck) { - return mem.data(); - } - if (addr < 0x80000000 || addr > 0x87ffffff) { - std::cerr << std::hex << "ACCESS " << addr << std::dec << std::endl; - throw std::runtime_error("Invalid memory access"); - } - // Linear mapping - return (uint8_t *)(mem.data() + (addr >> 2) - 0x20000000) + (addr & 0x3); - } - void trace(paddr_t addr, bool is_read, word_t pc = 0, word_t value = 0) { - for (auto &r : trace_ranges) { - if (r[0] <= addr && r[1] >= addr) { - std::stringstream os; - os << std::hex; - if (pc != 0) - os << "0x" << pc << " "; - if (is_read) - os << "[R] "; - else - os << "[W] " << value << " -> "; - os << "0x" << addr << std::dec << std::endl; - std::cout << os.rdbuf(); - break; - } - } + mem[addr_to_index((uint32_t)waddr)] = expand_bits(wmask) & wdata; } }; #endif diff --git a/npc/include/config.hpp b/npc/include/config.hpp index de536b6..9f5873c 100644 --- a/npc/include/config.hpp +++ b/npc/include/config.hpp @@ -3,17 +3,13 @@ #include #include #include -#include #include -#include struct Config { std::filesystem::path memory_file; - uint64_t max_sim_time = 0; + uint64_t max_sim_time = 1000; bool memory_file_binary = {true}; - bool do_mtrace{false}; - std::vector> mtrace_ranges{ - {0x80000000, 0x8ffffffff}}; + bool do_trace{false}; std::filesystem::path wavefile; std::filesystem::path lib_ref; void cli_parse(int argc, char **argv); diff --git a/npc/include/difftest.hpp b/npc/include/difftest.hpp new file mode 100644 index 0000000..7349004 --- /dev/null +++ b/npc/include/difftest.hpp @@ -0,0 +1,130 @@ +#ifndef _DIFFTEST_DIFFTEST_H_ +#define _DIFFTEST_DIFFTEST_H_ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +using paddr_t = uint32_t; +enum { DIFFTEST_FROM_REF, DIFFTEST_TO_REF }; + +struct DifftestInterface { + using memcpy_t = void (*)(paddr_t, void *, size_t, bool); + using regcpy_t = void (*)(void *, bool); + using exec_t = void (*)(uint64_t); + using init_t = void (*)(int); + std::function memcpy; + std::function regcpy; + std::function exec; + std::function init; + + DifftestInterface(memcpy_t memcpy, regcpy_t regcpy, exec_t exec, init_t init) + : memcpy(memcpy), regcpy(regcpy), exec(exec), init(init){}; + + // using fs = std::filesystem::path; + DifftestInterface(std::filesystem::path lib_file) { + void *handle = dlopen(lib_file.c_str(), RTLD_LAZY); + assert(handle != nullptr); + memcpy = (memcpy_t)dlsym(handle, "difftest_memcpy"); + assert(memcpy); + regcpy = (regcpy_t)dlsym(handle, "difftest_regcpy"); + assert(regcpy); + exec = (exec_t)dlsym(handle, "difftest_exec"); + assert(exec); + init = (init_t)dlsym(handle, "difftest_init"); + assert(init); + } +}; + +template class Difftest { + const DifftestInterface &ref; + std::unique_ptr ref_state; + const DifftestInterface &dut; + std::unique_ptr dut_state; + +public: + Difftest(const DifftestInterface &dut, const DifftestInterface &ref, + void *mem, size_t n, std::unique_ptr ref_state = nullptr, + std::unique_ptr dut_state = nullptr) + : ref(ref), dut(dut), ref_state(std::move(ref_state)), + dut_state(std::move(dut_state)) { + if (ref_state == nullptr) + this->ref_state = std::make_unique(); + if (dut_state == nullptr) + this->dut_state = std::make_unique(); + ref.init(0); + dut.init(0); + fetch_state(); + paddr_t reset_vector = 0x80000000; + ref.memcpy(reset_vector, mem, n, DIFFTEST_TO_REF); + dut.memcpy(reset_vector, mem, n, DIFFTEST_TO_REF); + }; + + void fetch_state() { + ref.regcpy(ref_state.get(), DIFFTEST_FROM_REF); + dut.regcpy(dut_state.get(), DIFFTEST_FROM_REF); + } + + bool step(uint64_t n) { + ref.exec(n); + dut.exec(n); + fetch_state(); + return *ref_state == *dut_state; + } + + friend std::ostream &operator<<(std::ostream &os, const Difftest &d) { + os << "REF state:\n" + << *d.ref_state << "DUT state:\n" + << *d.dut_state << std::endl; + return os; + } +}; + +template struct CPUStateBase { + R reg[nr_reg] = {0}; + paddr_t pc = 0x80000000; + static const std::map inline regs_by_name = + riscv32_regs_by_name; + CPUStateBase() { + for (int i = 0; i < nr_reg; i++) + reg[i] = 0; + } + bool operator==(const CPUStateBase &other) const { + if (pc != other.pc) + return false; + for (int i = 0; i < nr_reg; ++i) { + if (reg[i] != other.reg[i]) + return false; + } + return true; + } + bool operator!=(const CPUStateBase &other) const { + return !(*this == other); // Reuse the == operator for != implementation + } + + /* This does not update the register!!! */ + R at(std::string name) { return reg[regs_by_name.at(name)]; } +}; + +template +std::ostream &operator<<(std::ostream &os, const CPUStateBase &cpu) { + os << "PC: " << std::hex << cpu.pc << std::endl; + for (int i = 0; i < nr_reg; i++) { + os << "reg " << std::dec << std::setw(2) << i << ":" << std::hex + << std::setw(10) << cpu.reg[i]; + if (i % 4 == 3) { + os << std::endl; + } else { + os << " | "; + } + } + return os; +} + +#endif \ No newline at end of file diff --git a/npc/include/trm_difftest.hpp b/npc/include/trm_difftest.hpp deleted file mode 100644 index ef8bde0..0000000 --- a/npc/include/trm_difftest.hpp +++ /dev/null @@ -1,102 +0,0 @@ -#ifndef _DIFFTEST_DIFFTEST_H_ -#define _DIFFTEST_DIFFTEST_H_ -#include "disasm.hpp" -#include "types.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -using paddr_t = uint32_t; -struct DifftestTrmInterface : public TrmInterface { - TrmInterface &dut; - TrmInterface &ref; - - DifftestTrmInterface(TrmInterface &dut, TrmInterface &ref, void *mem, - size_t mem_size) - : dut(dut), ref(ref) { - init = [this, mem, mem_size](int n) { - this->ref.init(n); - this->dut.init(n); - paddr_t reset_vector = 0x80000000; - this->ref.memcpy(reset_vector, mem, mem_size, TRM_TO_MACHINE); - this->dut.memcpy(reset_vector, mem, mem_size, TRM_TO_MACHINE); - fetch_state(); - }; - exec = [this](uint64_t n) { - bool enable_disasm = true; - if (n > 30) { - enable_disasm = false; - } - - while (n--) { - word_t pc = this->ref.at("pc"); - word_t inst = this->ref.at(pc); - if (enable_disasm) - std::cout << d.disassemble(pc, (uint8_t *)&inst, WORD_BYTES) - << std::endl; - if (inst == 1048691) { - // ebreak - throw TrmRuntimeException(TrmRuntimeException::EBREAK, "ebreak"); - } - this->ref.exec(1); - this->dut.exec(1); - this->ref.fetch_state(); - this->dut.fetch_state(); - if (*(CPUState *)this->ref.cpu_state != - *(CPUState *)this->dut.cpu_state) { - throw TrmRuntimeException(TrmRuntimeException::DIFFTEST_FAILED, - "Difftest failed"); - } - } - }; - - // NOTE: Different from normal Trm, we copy 2 * sizeof(CPUState) to/from p, - // which represents ref_state and dut state - regcpy = [this](void *p, bool direction) { - // this->ref.regcpy(p, direction); - // this->dut.regcpy(p, direction); - }; - - memcpy = [this](paddr_t paddr, void *p, size_t n, bool direction) { - this->dut.memcpy(paddr, p, n, direction); - this->ref.memcpy(paddr, (uint8_t *)p + n, n, direction); - }; - } - - word_t at(std::string name) const override { - if (name.empty()) { - throw std::runtime_error("Empty register name"); - } else if (name[0] == 'r') { - std::cout << name.substr(1) << std::endl; - this->ref.at(name.substr(1)); - } else if (name[0] == 'd') { - this->dut.at(name.substr(1)); - } else { - throw std::runtime_error("Register name provided to difftest interface " - "must start with r or d."); - } - return 0; - } - - word_t at(paddr_t addr) const override { - std::cout << ref.at(addr) << "\t" << dut.at(addr) << std::endl; - return dut.at(addr); - } - - void print(std::ostream &os) const override { - os << "REF state:\n" - << *(CPUState *)ref.cpu_state << "DUT state:\n" - << *(CPUState *)dut.cpu_state << std::endl; - } -}; -#endif \ No newline at end of file diff --git a/npc/include/trm_interface.hpp b/npc/include/trm_interface.hpp deleted file mode 100644 index 5acb8d6..0000000 --- a/npc/include/trm_interface.hpp +++ /dev/null @@ -1,157 +0,0 @@ -#ifndef _NPC_TRM_INTERFACE_HEADER_FILE_ -#define _NPC_TRM_INTERFACE_HEADER_FILE_ -#include -#include -#include -#include -#include -#include -#include - -extern Disassembler d; - -template struct CPUStateBase { - R reg[nr_reg] = {0}; - word_t pc = 0x80000000; - - static const std::map inline regs_by_name = - riscv32_regs_by_name; - CPUStateBase() { - for (int i = 0; i < nr_reg; i++) - reg[i] = 0; - } - - bool operator==(const CPUStateBase &other) const { - if (pc != other.pc) - return false; - for (int i = 0; i < nr_reg; ++i) { - if (reg[i] != other.reg[i]) - return false; - } - return true; - } - - bool operator!=(const CPUStateBase &other) const { - return !(*this == other); // Reuse the == operator for != implementation - } - - /* This does not update the register!!! */ - R at(std::string name) { - return name == "pc" ? pc : reg[regs_by_name.at(name)]; - } - - uint32_t reg_str2val(const char *name, bool *success) { - try { - *success = true; - return this->at(name); - } catch (std::runtime_error) { - *success = false; - return 0; - } - } -}; - -template -std::ostream &operator<<(std::ostream &os, const CPUStateBase &cpu) { - os << "PC: " << std::hex << cpu.pc << std::endl; - for (int i = 0; i < nr_reg; i++) { - os << "reg " << std::dec << std::setw(2) << i << ":" << std::hex - << std::setw(10) << cpu.reg[i]; - if (i % 4 == 3) { - os << std::endl; - } else { - os << " | "; - } - } - return os; -} - -using CPUState = CPUStateBase; - -enum { TRM_FROM_MACHINE, TRM_TO_MACHINE }; - -class TrmInterface { -protected: - using memcpy_t = void (*)(paddr_t, void *, size_t, bool); - using regcpy_t = void (*)(void *, bool); - using exec_t = void (*)(uint64_t); - using init_t = void (*)(int); - std::function regcpy; - -public: - std::function exec; - std::function init; - // TODO: paddr_t can probably changed to (void *)? - std::function memcpy; - // Managed by callee - void *cpu_state; - - TrmInterface() {} - TrmInterface(memcpy_t f_memcpy, regcpy_t f_regcpy, exec_t f_exec, - init_t f_init, void *cpu_state) - : memcpy(f_memcpy), regcpy(f_regcpy), exec(f_exec), init(f_init), - cpu_state(cpu_state) {} - - void fetch_state() { this->regcpy(cpu_state, TRM_FROM_MACHINE); } - void push_state() { this->regcpy(cpu_state, TRM_TO_MACHINE); } - virtual word_t at(std::string) const = 0; - virtual word_t at(word_t addr) const = 0; - virtual void print(std::ostream &os) const = 0; -}; - -class TrmRuntimeException : public std::exception { -private: - const char *msg_; - int code_; - -public: - enum { EBREAK, DIFFTEST_FAILED }; - TrmRuntimeException(int code, const char *message) - : code_(code), msg_(message) {} - - virtual const char *what() const throw() { return msg_; } - - int error_code() const { return code_; } -}; - -struct RefTrmInterface : TrmInterface { - RefTrmInterface(std::filesystem::path lib_file) { - void *handle = dlopen(lib_file.c_str(), RTLD_LAZY); - if (handle == nullptr) { - throw std::runtime_error("Failed to open diff library file"); - }; - memcpy = (memcpy_t)dlsym(handle, "difftest_memcpy"); - if (handle == nullptr) { - throw std::runtime_error("Failed to find `difftest_memcpy`"); - }; - regcpy = (regcpy_t)dlsym(handle, "difftest_regcpy"); - if (handle == nullptr) { - throw std::runtime_error("Failed to find `difftest_regcpy`"); - }; - exec = (exec_t)dlsym(handle, "difftest_exec"); - if (handle == nullptr) { - throw std::runtime_error("Failed to find `difftest_exec`"); - }; - init = (init_t)dlsym(handle, "difftest_init"); - if (handle == nullptr) { - throw std::runtime_error("Failed to find `difftest_init`"); - }; - cpu_state = new CPUState{}; - } - - ~RefTrmInterface() { delete (CPUState *)cpu_state; } - - word_t at(std::string name) const override { - return ((CPUState *)cpu_state)->at(name); - } - - word_t at(paddr_t addr) const override { - word_t buf; - this->memcpy(addr, &buf, sizeof(word_t), TRM_FROM_MACHINE); - return buf; - } - - void print(std::ostream &os) const override { os << *(CPUState *)cpu_state; } -}; - -#endif \ No newline at end of file diff --git a/npc/include/types.h b/npc/include/types.h index 6f78cc1..f6a8d87 100644 --- a/npc/include/types.h +++ b/npc/include/types.h @@ -8,7 +8,6 @@ static const word_t WORD_T_MAX = UINT32_MAX; static const sword_t SWORD_T_MAX = INT32_MAX; static const sword_t SWORD_T_MIN = INT32_MIN; #define WORD_BYTES 4 -#define REG_COUNT 32 #define FMT_WORD "0x%08x" typedef uint32_t vaddr_t; @@ -17,16 +16,8 @@ typedef uint32_t paddr_t; typedef uint16_t ioaddr_t; #ifdef __cplusplus -#include -#include - -const std::map riscv32_regs_by_name{ - {"$0", 0}, {"ra", 1}, {"sp", 2}, {"gp", 3}, {"tp", 4}, {"t0", 5}, - {"t1", 6}, {"t2", 7}, {"s0", 8}, {"s1", 9}, {"a0", 10}, {"a1", 11}, - {"a2", 12}, {"a3", 13}, {"a4", 14}, {"a5", 15}, {"a6", 16}, {"a7", 17}, - {"s2", 18}, {"s3", 19}, {"s4", 20}, {"s5", 21}, {"s6", 22}, {"s7", 23}, - {"s8", 24}, {"s9", 25}, {"s10", 26}, {"s11", 27}, {"t3", 28}, {"t4", 29}, - {"t5", 30}, {"t6", 31}}; +#include +using CPUState = CPUStateBase; #endif #endif \ No newline at end of file diff --git a/npc/include/vl_wrapper.hpp b/npc/include/vl_wrapper.hpp index 61414c4..4d42b55 100644 --- a/npc/include/vl_wrapper.hpp +++ b/npc/include/vl_wrapper.hpp @@ -1,6 +1,5 @@ #ifndef _NPC_TRACER_H_ #define _NPC_TRACER_H_ -#include "components.hpp" #include #include @@ -32,8 +31,9 @@ template class VlModuleInterfaceCommon : public T { std::unique_ptr> tracer; public: - VlModuleInterfaceCommon(std::filesystem::path wavefile) { - if (!wavefile.empty()) + VlModuleInterfaceCommon(bool do_trace, + std::filesystem::path wavefile = "waveform.vcd") { + if (do_trace) tracer = std::make_unique>(this, wavefile); } void eval() { @@ -52,12 +52,9 @@ public: } } void reset_eval(int n) { - extern bool g_skip_memcheck; - g_skip_memcheck = true; this->reset = 1; this->eval(n); this->reset = 0; - g_skip_memcheck = false; } bool is_posedge() { // Will be posedge when eval is called diff --git a/npc/utils/CMakeLists.txt b/npc/utils/CMakeLists.txt index d61f3d8..017313c 100644 --- a/npc/utils/CMakeLists.txt +++ b/npc/utils/CMakeLists.txt @@ -1,3 +1,4 @@ +add_subdirectory(disasm) if (ENABLE_SDB) add_subdirectory(sdb) endif() diff --git a/npc/utils/disasm/CMakeLists.txt b/npc/utils/disasm/CMakeLists.txt new file mode 100644 index 0000000..e019bf7 --- /dev/null +++ b/npc/utils/disasm/CMakeLists.txt @@ -0,0 +1,4 @@ +add_library(disasm disasm.cpp) +target_include_directories(disasm PUBLIC include) +llvm_map_components_to_libnames(LLVM_LIBS ${LLVM_TARGETS_TO_BUILD}) +target_link_libraries(disasm PUBLIC ${LLVM_LIBS}) diff --git a/npc/utils/sdb/disasm.cpp b/npc/utils/disasm/disasm.cpp similarity index 89% rename from npc/utils/sdb/disasm.cpp rename to npc/utils/disasm/disasm.cpp index e4671f0..0e817ba 100644 --- a/npc/utils/sdb/disasm.cpp +++ b/npc/utils/disasm/disasm.cpp @@ -25,14 +25,11 @@ #endif Disassembler::Disassembler(std::string triple) : triple(triple) { - // llvm::InitializeAllTargetInfos(); - // llvm::InitializeAllTargetMCs(); - // llvm::InitializeAllAsmParsers(); - // llvm::InitializeAllDisassemblers(); - LLVMInitializeRISCVTargetInfo(); - LLVMInitializeRISCVTargetMC(); - LLVMInitializeRISCVAsmParser(); - LLVMInitializeRISCVDisassembler(); + llvm::InitializeAllTargetInfos(); + llvm::InitializeAllTargetMCs(); + llvm::InitializeAllAsmParsers(); + llvm::InitializeAllDisassemblers(); + std::string errstr; llvm::MCInstrInfo *gMII = nullptr; diff --git a/npc/utils/sdb/include/disasm.hpp b/npc/utils/disasm/include/disasm.hpp similarity index 100% rename from npc/utils/sdb/include/disasm.hpp rename to npc/utils/disasm/include/disasm.hpp diff --git a/npc/utils/sdb/CMakeLists.txt b/npc/utils/sdb/CMakeLists.txt index 2a41fbf..6b1cb2c 100644 --- a/npc/utils/sdb/CMakeLists.txt +++ b/npc/utils/sdb/CMakeLists.txt @@ -1,7 +1,6 @@ find_package(Readline REQUIRED) find_package(FLEX REQUIRED) find_package(BISON REQUIRED) -find_package(LLVM CONFIG REQUIRED) set(PARSER_DIR "${CMAKE_CURRENT_BINARY_DIR}") set(LEXER_OUT "${PARSER_DIR}/lexer.c") set(PARSER_OUT "${PARSER_DIR}/parser.c") @@ -9,10 +8,7 @@ flex_target(LEXER addrexp.l "${LEXER_OUT}" DEFINES_FILE "${PARSER_DIR}/addrexp_l bison_target(PARSER addrexp.y "${PARSER_OUT}" DEFINES_FILE "${PARSER_DIR}/addrexp.h") add_flex_bison_dependency(LEXER PARSER) -add_library(sdb OBJECT sdb.cpp console.cpp disasm.cpp "${LEXER_OUT}" "${PARSER_OUT}") -llvm_map_components_to_libnames(LLVM_LIBS core target asmparser riscvasmparser riscvdesc riscvdisassembler riscvinfo riscvtargetmca) -target_link_libraries(sdb PUBLIC ${LLVM_LIBS}) +add_library(sdb sdb.cpp console.cpp "${LEXER_OUT}" "${PARSER_OUT}") target_link_libraries(sdb PRIVATE ${Readline_LIBRARY}) -target_include_directories(sdb PRIVATE ${PARSER_DIR}) target_include_directories(sdb PRIVATE ${Readline_INCLUDE_DIR}) target_include_directories(sdb PUBLIC include) diff --git a/npc/utils/sdb/addrexp.y b/npc/utils/sdb/addrexp.y index 477d8dd..ca1a5c9 100644 --- a/npc/utils/sdb/addrexp.y +++ b/npc/utils/sdb/addrexp.y @@ -22,7 +22,6 @@ %parse-param { uint32_t *result } %left '-' '+' %left '*' '/' -%expect 68 %% input diff --git a/npc/utils/sdb/console.cpp b/npc/utils/sdb/console.cpp index 61c9452..485e192 100644 --- a/npc/utils/sdb/console.cpp +++ b/npc/utils/sdb/console.cpp @@ -83,12 +83,6 @@ void Console::registerCommand(const std::string &s, CommandFunction f) { pimpl_->commands_[s] = f; } -void Console::removeCommands(const std::vector sv) { - for (auto const &s : sv) { - pimpl_->commands_.erase(s); - } -} - std::vector Console::getRegisteredCommands() const { std::vector allCommands; for (auto &pair : pimpl_->commands_) diff --git a/npc/utils/sdb/include/console.hpp b/npc/utils/sdb/include/console.hpp index 69c4099..538ce2f 100644 --- a/npc/utils/sdb/include/console.hpp +++ b/npc/utils/sdb/include/console.hpp @@ -64,13 +64,6 @@ public: */ void registerCommand(const std::string &s, CommandFunction f); - /** - * @brief This function removes a list of registered commands. - * - * @param sv The vector of command names to be removed. - */ - void removeCommands(const std::vector sv); - /** * @brief This function returns a list with the currently available commands. * diff --git a/npc/utils/sdb/include/sdb.hpp b/npc/utils/sdb/include/sdb.hpp index 964412a..18aae8a 100644 --- a/npc/utils/sdb/include/sdb.hpp +++ b/npc/utils/sdb/include/sdb.hpp @@ -3,10 +3,9 @@ #include #include +#include #include #include -#include -#include #include namespace cr = CppReadline; @@ -16,81 +15,132 @@ namespace SDB { enum SDBStatus { SDB_SUCCESS, - SDB_EBREAK = 2, SDB_WRONG_ARGUMENT, - SDB_DIFFTEST_FAILED }; -class SDBHandlers; - struct Handler { const std::vector names; - // cr::Console::CommandFunction f; - std::function f; + cr::Console::CommandFunction f; }; -class SDBHandlers { +template class _SDBHandlers { + using CPUState = CPUStateBase; + private: - const TrmInterface &funcs; - std::vector all_handlers = { - Handler{{"c", "continue"}, &SDBHandlers::cmd_continue}, - Handler{{"si", "step-instruction"}, &SDBHandlers::cmd_step}, - Handler{{"info-r"}, &SDBHandlers::cmd_info_registers}, - Handler{{"p", "print"}, &SDBHandlers::cmd_print}, - Handler{{"disas", "disassemble"}, &SDBHandlers::cmd_disassemble}, - }; - int cmd_continue(const cr::Console::Arguments &input); - int cmd_step(const std::vector &input); - int cmd_info_registers(const std::vector &input); - int cmd_print(const std::vector &input); - int cmd_disassemble(const std::vector &input); - int exec_catch(uint64_t); + std::vector all_handlers; public: - SDBHandlers(const TrmInterface &funcs) : funcs(funcs){}; - void register_handlers(cr::Console *c); + static CPUState cpu; + +private: + static _SDBHandlers *instance; + static int cmd_continue(const cr::Console::Arguments &input); + static int cmd_step(const std::vector &input); + static int cmd_info_registers(const std::vector &input); + static int cmd_print(const std::vector &input); + _SDBHandlers(std::vector all_handlers) + : all_handlers(all_handlers){}; + +public: + _SDBHandlers(const _SDBHandlers &) = delete; + _SDBHandlers operator=(const _SDBHandlers &) = delete; + + static _SDBHandlers *getInstance() { + if (instance == nullptr) { + std::vector all_handlers{ + Handler{{"c", "continue"}, &_SDBHandlers::cmd_continue}, + Handler{{"si", "step-instruction"}, &_SDBHandlers::cmd_step}, + }; + instance = new _SDBHandlers(all_handlers); + } + return instance; + } + + void registerHandlers(cr::Console *c); }; -class SDB { +template +_SDBHandlers *_SDBHandlers::instance = nullptr; + +template +CPUState _SDBHandlers::cpu = CPUState(); + +template +int _SDBHandlers::cmd_continue(const cr::Console::Arguments &input) { + if (input.size() > 1) + return SDB_WRONG_ARGUMENT; + funcs.exec(-1); + return SDB_SUCCESS; +} + +template +int _SDBHandlers::cmd_step(const std::vector &input) { + if (input.size() > 2) { + return SDB_WRONG_ARGUMENT; + } + uint64_t step_count = input.size() == 2 ? std::stoull(input[1]) : 1; + funcs.exec(step_count); + return SDB_SUCCESS; +} + +template +int _SDBHandlers::cmd_info_registers( + const std::vector &input) { + if (input.size() > 1) + return SDB_WRONG_ARGUMENT; + std::cout << _SDBHandlers::getInstance()->cpu << std::endl; + return SDB_SUCCESS; +} + +template +int _SDBHandlers::cmd_print(const std::vector &input) { + exit(1); +} + +template +void _SDBHandlers::registerHandlers(cr::Console *c) { + for (auto &h : this->all_handlers) { + for (auto &name : h.names) { + c->registerCommand(name, h.f); + } + } +} + +template class SDB { private: std::unique_ptr c; - const TrmInterface &funcs; - SDBHandlers handlers; + using SDBHandlers = _SDBHandlers; public: - SDB(const TrmInterface &funcs, - std::string const &greeting = "\033[1;34m(npc)\033[0m ") - : handlers(SDBHandlers{funcs}), funcs(funcs) { + SDB(std::string const &greeting = "\033[1;34m(npc)\033[0m ") { c = std::make_unique(greeting); - - handlers.register_handlers(c.get()); + SDBHandlers::getInstance()->registerHandlers(c.get()); }; + word_t reg_str2val(const char *name, bool *success) { + try { + *success = true; + return SDBHandlers::getInstance()->cpu.at(name); + } catch (std::runtime_error) { + *success = false; + return 0; + } + } + int main_loop() { - int ret_code; - funcs.init(0); - std::vector step_commands{"c", "continue", "si", - "step-instruction"}; + int retCode; do { - ret_code = c->readLine(); + retCode = c->readLine(); // We can also change the prompt based on last return value: - if (ret_code == SDB_SUCCESS || ret_code == SDB_EBREAK) + if (retCode == ret::Ok) c->setGreeting("\033[1;34m(npc)\033[0m "); else c->setGreeting("\033[1;31m(npc)\033[0m "); - switch (ret_code) { - case SDB_EBREAK: { - std::cout << "\033[1;31m=== ebreak ===\033[0m" << std::endl; - c->removeCommands(step_commands); - break; + if (retCode == SDB_WRONG_ARGUMENT) { + std::cout << "Wrong argument give to command\n"; } - case SDB_WRONG_ARGUMENT: { - std::cout << "Wrong argument(s) is given to command handler\n"; - break; - } - } - } while (ret_code != ret::Quit); + } while (retCode != ret::Quit); return 0; } }; diff --git a/npc/utils/sdb/sdb.cpp b/npc/utils/sdb/sdb.cpp index 55d6d41..9bfa6b5 100644 --- a/npc/utils/sdb/sdb.cpp +++ b/npc/utils/sdb/sdb.cpp @@ -1,114 +1,10 @@ #include #include -#include -#include +#include #include -#include -#include #include -extern "C" { -#include -#include -} namespace cr = CppReadline; using ret = cr::Console::ReturnCode; -std::ostream &operator<<(std::ostream &os, const TrmInterface &d) { - d.print(os); - return os; -}; - -Disassembler d{"riscv32-linux-pc-gnu"}; - -namespace SDB { - -int SDBHandlers::exec_catch(uint64_t n) { - try { - this->funcs.exec(n); - } catch (TrmRuntimeException &e) { - switch (e.error_code()) { - case TrmRuntimeException::EBREAK: - return SDB_EBREAK; - case TrmRuntimeException::DIFFTEST_FAILED: - std::cout << "Difftest Failed" << std::endl << funcs << std::endl; - return SDB_DIFFTEST_FAILED; - default: - std::cerr << "Unknown error code" << std::endl; - exit(1); - } - } - return SDB_SUCCESS; -} - -int SDBHandlers::cmd_continue(const cr::Console::Arguments &input) { - if (input.size() > 1) - return SDB_WRONG_ARGUMENT; - return exec_catch(-1); -} - -int SDBHandlers::cmd_step(const std::vector &input) { - if (input.size() > 2) { - return SDB_WRONG_ARGUMENT; - } - uint64_t step_count = input.size() == 2 ? std::stoull(input[1]) : 1; - return exec_catch(step_count); - // std::cout << funcs << std::endl; -} - -int SDBHandlers::cmd_info_registers(const std::vector &input) { - if (input.size() > 1) - return SDB_WRONG_ARGUMENT; - std::cout << this->funcs << std::endl; - return SDB_SUCCESS; -} - -word_t parse_expr(const char *arg) { - if (arg == NULL) { - puts("Invalid expr argument."); - return 0; - } else { - word_t res; - yy_scan_string(arg); - yyparse(&res); - yylex_destroy(); - return res; - } -} - -int SDBHandlers::cmd_print(const std::vector &input) { - word_t buf[2]; - word_t addr = parse_expr(input[1].c_str()); - this->funcs.memcpy(addr, &buf, sizeof(word_t), TRM_FROM_MACHINE); - // TODO: Difftest only - std::cout << std::hex << "dut: 0x" << buf[0] << ' ' << "ref: 0x" << buf[1] - << std::dec << std::endl; - return SDB_SUCCESS; -} - -int SDBHandlers::cmd_disassemble(const std::vector &input) { - word_t buf[2]; - word_t addr = parse_expr(input[1].c_str()); - this->funcs.memcpy(addr, &buf, sizeof(word_t), TRM_FROM_MACHINE); - // TODO: Difftest only - std::cout << "dut: \n" - << d.disassemble(addr, (uint8_t *)&buf[0], sizeof(word_t)) - << std::endl - << "ref: \n" - << d.disassemble(addr, (uint8_t *)&buf[0], sizeof(word_t)) - << std::endl; - ; - return SDB_SUCCESS; -} - -void SDBHandlers::register_handlers(cr::Console *c) { - for (auto &h : this->all_handlers) { - for (auto &name : h.names) { - std::function)> f{ - std::bind(h.f, this, std::placeholders::_1)}; - c->registerCommand(name, f); - } - } -} - -} // namespace SDB +namespace SDB {}