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Author SHA1 Message Date
f5335c21f1
npc,fix: bugs of new arch in cpu-tests
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2024-09-06 15:10:35 +08:00

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@ -94,7 +94,6 @@ class newALU(implicit p: Params) extends Module {
val b = Input(Vec(SrcBSelect.all.length, UInt(p.XLEN)))
})
val out = IO(new Bundle {
val isEqual = Output(Bool())
val result = Output(UInt(p.XLEN))
})
@ -113,7 +112,6 @@ class newALU(implicit p: Params) extends Module {
val sll = a << b(5, 0)
val srl = a >> b(5, 0)
val sra = a.asSInt >> b(5, 0)
out.isEqual := a === b
import OpSelect._