> configure(npc)

ysyx_22040000 李心杨
 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar  1 12:35:11 UTC 2024 x86_64 GNU/Linux
  11:54:52  up 2 days  2:45,  2 users,  load average: 2.66, 1.60, 1.17

npc/core/build.sbt

@@ -6,10 +6,11 @@ val chiselVersion = "5.1.0"
 
 lazy val root = (project in file("."))
   .settings(
-    name := "ChiselLearning",
+    name := "flow",
     libraryDependencies ++= Seq(
       "org.chipsalliance" %% "chisel" % chiselVersion,
-      "edu.berkeley.cs" %% "chiseltest" % "5.0.2" % "test"
+      "edu.berkeley.cs" %% "chiseltest" % "5.0.2" % "test",
+      "com.chuusai" %% "shapeless" % "2.3.3"
     ),
     scalacOptions ++= Seq(
       "-language:reflectiveCalls",

npc/core/src/main/scala/ALU.scala

@@ -3,17 +3,21 @@ package npc.util
 import chisel3._
 import chisel3.util._
 
-class ALUGenerator(width: Int) extends Module {
+object ALUSel extends ChiselEnum {
-  require(width >= 0)
+  val add, sub, not, and, or, xor, slt, eq, nop = Value
+}
+
+class ALUGenerator[T <: ChiselEnum](width: Int, tpe: T = ALUSel) extends Module {
   val io = IO(new Bundle {
-    val a = Input(UInt(width.W))
+    val a = Input(UInt(tpe.getWidth.W))
-    val b = Input(UInt(width.W))
+    val b = Input(UInt(tpe.getWidth.W))
-    val op = Input(UInt(4.W))
+    val op = Input(ALUSel())
-    val out = Output(UInt(width.W))
+    val out = Output(UInt(tpe.getWidth.W))
   })
 
-  val adder_b = (Fill(width, io.op(0)) ^ io.b) + io.op(0)  // take (-b) if sub
+  // val adder_b = (Fill(tpe.getWidth, io.op(0)) ^ io.b) + io.op(0)  // take (-b) if sub
-  val add = io.a + adder_b
+  val add = io.a + io.b 
+  val sub = io.a - io.b
   val and = io.a & io.b
   val not = ~io.a
   val or = io.a | io.b
@@ -21,14 +25,14 @@ class ALUGenerator(width: Int) extends Module {
   val slt = io.a < io.b
   val eq = io.a === io.b
 
-  io.out := MuxLookup(io.op, 0.U)(Seq(
+  io.out := MuxLookup(io.op, ALUSel.nop.asUInt)(Seq(
-    0.U -> add,
+    ALUSel.add -> add,
-    1.U -> add, // add with b reversed
+    ALUSel.sub -> sub,
-    2.U -> not,
+    ALUSel.not -> not,
-    3.U -> and,
+    ALUSel.and -> and,
-    4.U -> or,
+    ALUSel.or  -> or,
-    5.U -> xor,
+    ALUSel.xor -> xor,
-    6.U -> slt,
+    ALUSel.slt -> slt,
-    7.U -> eq,
+    ALUSel.eq -> eq
   ))
 }

npc/core/src/main/scala/Main.scala

@@ -1,9 +1,18 @@
 package npc
 
+import scala.reflect.runtime.universe._
 import chisel3._
 import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
+import chisel3.util.{SRAM}
+import chisel3.util.experimental.decode.{decoder, TruthTable, QMCMinimizer}
 import chisel3.stage.ChiselOption
-import npc.util.KeyboardSegController
+import npc.util.{ KeyboardSegController }
+import flowpc.components.RegisterFile
+import chisel3.util.log2Ceil
+import chisel3.util.BitPat
+import chisel3.util.Enum
+import chisel3.experimental.prefix
+import shapeless.{ HNil, :: }
 
 class Switch extends Module {
   val io = IO(new Bundle {
@@ -31,3 +40,58 @@ class Keyboard extends Module {
   io.segs := seg_handler.io.segs
 }
 
+object RV32Inst {
+  private val bp = BitPat
+  val addi = this.bp("b??b?????_?????_?????_000_?????_00100_11")
+  val inv = this.bp("b???????_?????_?????_???_?????_?????_??")
+}
+
+class PcControl(width: Int) extends Bundle {
+  object SrcSelect extends ChiselEnum {
+      val pPC, pExeResult = Value
+  }
+  val srcSelect = Output(SrcSelect())
+}
+
+
+import flowpc.components.{ RegisterFile }
+class Control(width: Int) extends Module {
+  val reg = Flipped(RegisterFile(32, UInt(32.W), 2, 2))
+  val pc = new PcControl(width)
+  val inst = IO(Input(UInt(width.W)))
+
+  type T = Bool :: reg.control.WriteSelect.Type :: HNil
+  val dst: T = reg.control.writeEnable :: reg.control.writeSelect :: HNil
+  val dstList: List[Data] = dst.toList
+  val reversePrefixSum = dstList.scanLeft(0)(_ + _.getWidth).reverse
+  val slices = reversePrefixSum.zip(reversePrefixSum.tail)
+
+  import reg.control.WriteSelect._
+  import pc.SrcSelect._
+  import RV32Inst._
+  val ControlMapping: Array[(BitPat, T)] = Array(
+    //     Regs                       :: PC          :: Exe
+    //     writeEnable :: writeSelect :: srcSelect   :: 
+    (addi, false.B     :: rAluOut     ::               HNil)
+  )
+
+  def toBits(t: T): BitPat = {
+    val list: List[Data] = t.toList
+    list.map(x => x.asUInt).map(x => BitPat(x)).reduce(_ ## _)
+  }
+
+  val out = decoder(QMCMinimizer, inst, TruthTable(
+    ControlMapping.map(it => (it._1, toBits(it._2))), inv))
+  val srcList = slices.map(s => out(s._1 - 1, s._2))
+  srcList.zip(dstList).foreach({ case (src, dst) => dst := src })
+}
+
+class Flowpc extends Module {
+  val io = IO(new Bundle { })
+  val ram = SRAM(size=128*1024*1024, tpe=UInt(32.W), numReadPorts=2, numWritePorts=1,numReadwritePorts=0)
+
+  // Instruction Fetch
+  ram.readPorts(0).enable := true.B
+  val instruction = ram.readPorts(0).address
+
+}

npc/core/src/main/scala/ProgramCounter.scala

@@ -0,0 +1,13 @@
+package flowpc.components
+import chisel3._
+import chisel3.util.{Valid, log2Ceil}
+import chisel3.util.MuxLookup
+
+class ProgramCounter[T <: Data](tpe: T, numPcSrc: Int)  extends Module {
+  val io = new Bundle {
+    val pc_srcs = Input(Vec(numPcSrc, tpe))
+    val select = Input(UInt(log2Ceil(numPcSrc).W))
+    val pc = Output(tpe)
+  }
+    io.pc := io.pc_srcs(io.select)
+}

npc/core/src/main/scala/RegisterFile.scala

@@ -1,25 +1,72 @@
-package npc.util
+package flowpc.components
 
 import chisel3._
+import chisel3.util.log2Ceil
+import chisel3.util.UIntToOH
+import chisel3.util.MuxLookup
 
-class RegisterFile(readPorts: Int) extends Module {
+class RegControl extends Bundle {
-  require(readPorts >= 0)
+  val writeEnable = Input(Bool()) 
-  val io = IO(new Bundle {
-    val writeEnable = Input(Bool())
-    val writeAddr = Input(UInt(5.W))
-    val writeData = Input(UInt(32.W))
-    val readAddr = Input(Vec(readPorts, UInt(5.W)))
-    val readData = Output(Vec(readPorts, UInt(32.W)))
-  })
 
-  val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W))))
+  object WriteSelect extends ChiselEnum {
-  for (i <- 1 until 32) {
+    val rAluOut, rMemOut = Value
-    regFile(i) := regFile(i)
   }
-  regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr))
+  val writeSelect = Input(WriteSelect())
-  regFile(0) := 0.U
+}
 
-  for (i <- 0 until readPorts) {
+class RegFileData[T <: Data](size:Int, tpe: T, numReadPorts: Int, numWritePorts: Int) extends Bundle {
-    io.readData(i) := regFile(io.readAddr(i))
+  val write = new Bundle {
+    val addr = Input(UInt(size.W))
+    val data = Vec(numWritePorts, Input(tpe))
+  }
+  val read = Vec(numReadPorts, new Bundle {
+    val rs = Input(UInt(size.W))
+    val src = Output(tpe)
+  })
+}
+
+class RegFileInterface[T <: Data](size: Int, tpe: T, numReadPorts: Int, numWritePorts: Int) extends Bundle {
+  val control = new RegControl
+  val data = new RegFileData(size, tpe, numReadPorts, numWritePorts)
+}
+
+class RegisterFileCore[T <: Data](size: Int, tpe: T, numReadPorts: Int) extends Module {
+  printf("$numReadPorts\n")
+  require(numReadPorts >= 0)
+  val writePort = IO(new Bundle {
+    val enable = Input(Bool())
+    val addr = Input(UInt(size.W))
+    val data = Input(tpe)
+  })
+  val readPorts = IO(Vec(numReadPorts, new Bundle {
+    val addr = Input(UInt(size.W))
+    val data = Output(tpe)
+  }))
+
+  // val regFile = RegInit(VecInit(Seq.fill(size)(0.U)))
+  // val writeAddrOH = UIntToOH(writePort.addr)
+  // for ((reg, i) <- regFile.zipWithIndex) {
+  //   reg := Mux(writeAddrOH(i) && writePort.enable, writePort.data, reg)
+  // }
+
+  // for (readPort <- readPorts) {
+  //   readPort.data := regFile(readPort.addr)
+  // }
+}
+
+object RegisterFile {
+  def apply[T <: Data](size: Int, tpe: T, numReadPorts: Int, numWritePorts: Int): RegFileInterface[T] = {
+    val core = new RegisterFileCore(size, tpe, numReadPorts)
+    val _out = Wire(new RegFileInterface(size, tpe, numReadPorts, numWritePorts))
+    val clock = core.clock
+    for (i <- 0 to numReadPorts) {
+      core.readPorts(i).addr := _out.data.read(i).rs
+      core.readPorts(i).data := _out.data.read(i).src
+    }
+    core.writePort.addr := _out.data.write.addr
+    core.writePort.data := MuxLookup(_out.control.writeSelect, 0.U)(
+      _out.control.WriteSelect.all.map(x => (x -> _out.data.write.data(x.asUInt).asUInt))
+    )
+    _out
   }
 }

npc/core/src/test/scala/Main.scala

@@ -7,99 +7,64 @@ import chiseltest.simulator.WriteVcdAnnotation
 
 import npc.util._
 
-class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
+// class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
-  "RegisterFile should work" - {
+//   "With 32 width, " - {
-    "with 2 read ports" in {
+//     val neg = (x: BigInt) => BigInt("FFFFFFFF", 16) - x + 1
-      test(new RegisterFile(2)) { c =>
+//     val not = (x: BigInt) => x ^ BigInt("FFFFFFFF", 16)
-        def readExpect(addr: Int, value: Int, port: Int = 0): Unit = {
+//     val mask = BigInt("FFFFFFFF", 16)
-          c.io.readAddr(port).poke(addr.U)
+//     val oprands: List[(BigInt, BigInt)] = List(
-          c.io.readData(port).expect(value.U)
+//       (5, 3), (101010, 101010), (0xFFFFFFFCL, 0xFFFFFFFFL), (4264115, 2)
-        }
+//     )
-        def write(addr: Int, value: Int): Unit = {
+//     val operations: Map[Int, (BigInt, BigInt) => BigInt] = Map(
-          c.io.writeEnable.poke(true.B)
+//       0 -> ((a: BigInt, b: BigInt) => (a + b) & mask),
-          c.io.writeData.poke(value.U)
+//       1 -> ((a: BigInt, b: BigInt) => (a + neg(b)) & mask),
-          c.io.writeAddr.poke(addr.U)
+//       2 -> ((a, _) => not(a)),
-          c.clock.step(1)
+//       3 -> (_ & _),
-          c.io.writeEnable.poke(false.B)
+//       4 -> (_ | _),
-        }
+//       5 -> (_ ^ _),
-        // everything should be 0 on init
+//       6 -> ((a, b) => if (a < b) 1 else 0),
-        for (i <- 0 until 32) {
+//       7 -> ((a, b) => if (a == b) 1 else 0),
-          readExpect(i, 0, port = 0)
+//     )
-          readExpect(i, 0, port = 1)
+//     val validate = (c: ALUGenerator[32], op: Int, oprands: List[(BigInt, BigInt)]) => {
-        }
+//       c.io.op.poke(op.U)
-
+//       oprands.foreach({ case (a, b) =>
-        // write 5 * addr + 3
+//         c.io.a.poke(a.U)
-        for (i <- 0 until 32) {
+//         c.io.b.poke(b.U)
-          write(i, 5 * i + 3)
+//         c.io.out.expect(operations(op)(a, b))
-        }
+//       })
-
+//     }
-        // check that the writes worked
+//     "add should work" in {
-        for (i <- 0 until 32) {
+//       test(new ALUGenerator(32)) { c => validate(c, 0, oprands) }
-          readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2)
+//     }
-        }
+//     "sub should work" - {
-      }
+//       "with positive result" in {
-    }
+//         test(new ALUGenerator(32)) { c =>
-  }
+//           validate(c, 1, oprands.filter({case (a, b) => a >= b}))
-}
+//         }
-
+//       }
-class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
+//       "with negative result" in {
-  "With 32 width, " - {
+//         test(new ALUGenerator(32)) { c =>
-    val neg = (x: BigInt) => BigInt("FFFFFFFF", 16) - x + 1
+//           validate(c, 1, oprands.filter({case (a, b) => a < b}))
-    val not = (x: BigInt) => x ^ BigInt("FFFFFFFF", 16)
+//         }
-    val mask = BigInt("FFFFFFFF", 16)
+//       }
-    val oprands: List[(BigInt, BigInt)] = List(
+//     }
-      (5, 3), (101010, 101010), (0xFFFFFFFCL, 0xFFFFFFFFL), (4264115, 2)
+//     "not should work" in {
-    )
+//       test(new ALUGenerator(32)) { c => validate(c, 2, oprands) }
-    val operations: Map[Int, (BigInt, BigInt) => BigInt] = Map(
+//     }
-      0 -> ((a: BigInt, b: BigInt) => (a + b) & mask),
+//     "and should work" in {
-      1 -> ((a: BigInt, b: BigInt) => (a + neg(b)) & mask),
+//       test(new ALUGenerator(32)) { c => validate(c, 3, oprands) }
-      2 -> ((a, _) => not(a)),
+//     }
-      3 -> (_ & _),
+//     "or should work" in {
-      4 -> (_ | _),
+//       test(new ALUGenerator(32)) { c => validate(c, 4, oprands) }
-      5 -> (_ ^ _),
+//     }
-      6 -> ((a, b) => if (a < b) 1 else 0),
+//     "xor should work" in {
-      7 -> ((a, b) => if (a == b) 1 else 0),
+//       test(new ALUGenerator(32)) { c => validate(c, 5, oprands) }
-    )
+//     }
-    val validate = (c: ALUGenerator,op: Int, oprands: List[(BigInt, BigInt)]) => {
+//     "compare should work" in {
-      c.io.op.poke(op.U)
+//       test(new ALUGenerator(32)) { c => validate(c, 6, oprands) }
-      oprands.foreach({ case (a, b) =>
+//     }
-        c.io.a.poke(a.U)
+//     "equal should work" in {
-        c.io.b.poke(b.U)
+//       test(new ALUGenerator(32)) { c => validate(c, 7, oprands) }
-        c.io.out.expect(operations(op)(a, b))
+//     }
-      })
+//   }
-    }
+// }
-    "add should work" in {
-      test(new ALUGenerator(32)) { c => validate(c, 0, oprands) }
-    }
-    "sub should work" - {
-      "with positive result" in {
-        test(new ALUGenerator(32)) { c =>
-          validate(c, 1, oprands.filter({case (a, b) => a >= b}))
-        }
-      }
-      "with negative result" in {
-        test(new ALUGenerator(32)) { c =>
-          validate(c, 1, oprands.filter({case (a, b) => a < b}))
-        }
-      }
-    }
-    "not should work" in {
-      test(new ALUGenerator(32)) { c => validate(c, 2, oprands) }
-    }
-    "and should work" in {
-      test(new ALUGenerator(32)) { c => validate(c, 3, oprands) }
-    }
-    "or should work" in {
-      test(new ALUGenerator(32)) { c => validate(c, 4, oprands) }
-    }
-    "xor should work" in {
-      test(new ALUGenerator(32)) { c => validate(c, 5, oprands) }
-    }
-    "compare should work" in {
-      test(new ALUGenerator(32)) { c => validate(c, 6, oprands) }
-    }
-    "equal should work" in {
-      test(new ALUGenerator(32)) { c => validate(c, 7, oprands) }
-    }
-  }
-}

npc/core/src/test/scala/RegisterFile.scala

@@ -0,0 +1,29 @@
+package flowpc
+
+import chisel3._
+import chiseltest._
+import org.scalatest.freespec.AnyFreeSpec
+import chiseltest.simulator.WriteVcdAnnotation
+
+import flowpc.components._
+
+class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
+  "RegisterFileCore" - {
+    "(0) is always 0" - {
+      // val reg = new RegisterFileCore(32, UInt(32.W), 2)
+      test(new RegisterFileCore(32, UInt(32.W), 2)).withAnnotations(Seq(WriteVcdAnnotation)) { c => 
+        c.readPorts(0).addr.poke(0)
+        c.readPorts(1).addr.poke(0)
+        c.writePort.enable.poke(true)
+        c.writePort.addr.poke(0)
+        c.writePort.data.poke(0xdeadbeef)
+
+        c.readPorts(0).data.expect(0)
+        c.readPorts(1).data.expect(0)
+        c.clock.step(1)
+        c.readPorts(0).data.expect(0)
+        c.readPorts(1).data.expect(0)
+      }
+    }
+  }
+}

npc/flake.nix

@@ -19,6 +19,7 @@
           packages = [
             clang-tools
             rnix-lsp
+            coursier
 
             gdb
             jre