> configure(npc)
ysyx_22040000 李心杨 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux 18:42:28 up 2 days 17:43, 2 users, load average: 1.11, 0.95, 0.90
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tracer-ysyx
parent
b8d0ecf1b3
commit
f44cedc71d
10 changed files with 163 additions and 241 deletions
34
npc/core/src/main/scala/ALU.scala
Normal file
34
npc/core/src/main/scala/ALU.scala
Normal file
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@ -0,0 +1,34 @@
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package npc.util
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import chisel3._
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import chisel3.util._
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class ALUGenerator(width: Int) extends Module {
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require(width >= 0)
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val io = IO(new Bundle {
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val a = Input(UInt(width.W))
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val b = Input(UInt(width.W))
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val op = Input(UInt(4.W))
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val out = Output(UInt(width.W))
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})
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val adder_b = (Fill(width, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub
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val add = io.a + adder_b
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val and = io.a & io.b
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val not = ~io.a
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val or = io.a | io.b
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val xor = io.a ^ io.b
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val slt = io.a < io.b
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val eq = io.a === io.b
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io.out := MuxLookup(io.op, 0.U)(Seq(
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0.U -> add,
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1.U -> add, // add with b reversed
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2.U -> not,
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3.U -> and,
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4.U -> or,
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5.U -> xor,
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6.U -> slt,
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7.U -> eq,
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))
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}
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@ -1,10 +1,7 @@
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package npc.keyboard
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package npc.util
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import chisel3._
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import chisel3.util.{Counter, Decoupled, Queue, Reverse, MuxLookup, RegEnable}
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import npc.seg._
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import upickle.implicits.key
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import chisel3.util.{Counter, Decoupled, Queue, Reverse, MuxLookup}
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class PS2Port extends Bundle {
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val clk = Input(Bool())
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@ -56,49 +53,3 @@ class KeyboardController extends Module {
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received := false.B
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}
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}
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class SegGenerator(seg_count: Int) extends Module {
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val io = IO(new Bundle {
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val keycode = Flipped(Decoupled(UInt(8.W)))
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val segs = Output(Vec(seg_count, UInt(8.W)))
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})
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io.keycode.ready := false.B
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when(io.keycode.valid) {
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io.keycode.ready := true.B
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}
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val seg_regs = RegInit(VecInit(Seq.fill(seg_count)(0.U(8.W))))
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val last_keycode = RegInit(0.U(8.W))
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val digit_to_seg = ((0 until 16).map(_.U)).zip(Seq(
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"b00000011".U, "b10011111".U, "b00100101".U, "b00001101".U,
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"b10011001".U, "b01001001".U, "b01000001".U, "b00011111".U,
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"b00000001".U, "b00001001".U, "b00010001".U, "b11000001".U,
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"b01100011".U, "b10000101".U, "b01100001".U, "b01110001".U,
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))
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val keycode_to_ascii = Seq(
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0x1C.U, 0x32.U, 0x21.U, 0x23.U, 0x24.U, 0x2B.U,
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0x34.U, 0x33.U, 0x43.U, 0x3B.U, 0x42.U, 0x4B.U,
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0x3A.U, 0x31.U, 0x44.U, 0x4D.U, 0x15.U, 0x2D.U,
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0x1B.U, 0x2C.U, 0x3C.U, 0x2A.U, 0x1D.U, 0x22.U,
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0x35.U, 0x1A.U, 0x45.U, 0x16.U, 0x1E.U, 0x26.U,
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0x25.U, 0x2E.U, 0x36.U, 0x3D.U, 0x3E.U, 0x46.U,
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).zip(((0x41 to 0x5A) ++ (0x30 to 0x39)).map(_.U))
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// val keycode = Mux(io.keycode.ready && io.keycode.valid, io.keycode.bits, keycode)
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val keycode = RegEnable(io.keycode.bits, io.keycode.ready && io.keycode.valid)
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val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4))
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val keycode_seg = keycode_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
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val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii)
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val ascii_digits = VecInit(ascii(3,0)) ++ VecInit(ascii(6,4))
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val ascii_seg = ascii_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
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val (counter, _) = Counter(io.keycode.valid && io.keycode.ready && io.keycode.bits =/= keycode, 0xFF)
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val count_digits = VecInit(counter(3,0)) ++ VecInit(counter(7,4))
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val count_seg = count_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
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seg_regs := keycode_seg ++ ascii_seg ++ count_seg ++ Seq(0xFF.U, 0xFF.U)
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io.segs := seg_regs
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}
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@ -4,73 +4,6 @@ import chisel3._
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import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
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import chisel3.stage.ChiselOption
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class RegisterFile(readPorts: Int) extends Module {
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require(readPorts >= 0)
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val io = IO(new Bundle {
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val writeEnable = Input(Bool())
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val writeAddr = Input(UInt(5.W))
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val writeData = Input(UInt(32.W))
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val readAddr = Input(Vec(readPorts, UInt(5.W)))
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val readData = Output(Vec(readPorts, UInt(32.W)))
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})
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val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W))))
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for (i <- 1 until 32) {
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regFile(i) := regFile(i)
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}
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regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr))
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regFile(0) := 0.U
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for (i <- 0 until readPorts) {
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io.readData(i) := regFile(io.readAddr(i))
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}
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}
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class ALUGenerator(width: Int) extends Module {
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require(width >= 0)
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val io = IO(new Bundle {
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val a = Input(UInt(width.W))
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val b = Input(UInt(width.W))
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val op = Input(UInt(4.W))
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val out = Output(UInt(width.W))
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})
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val adder_b = (Fill(width, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub
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val add = io.a + adder_b
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val and = io.a & io.b
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val not = ~io.a
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val or = io.a | io.b
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val xor = io.a ^ io.b
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val slt = io.a < io.b
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val eq = io.a === io.b
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io.out := MuxLookup(io.op, 0.U)(Seq(
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0.U -> add,
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1.U -> add, // add with b reversed
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2.U -> not,
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3.U -> and,
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4.U -> or,
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5.U -> xor,
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6.U -> slt,
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7.U -> eq,
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))
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}
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class Test extends Module {
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val io = IO(new Bundle {
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val in = Input(UInt(32.W))
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val out = Output(UInt(32.W))
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})
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val regFile = Module(new RegisterFile(2))
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regFile.io.writeEnable := true.B
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regFile.io.writeAddr := 1.U
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regFile.io.writeData := io.in
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regFile.io.readAddr(0) := 0.U
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regFile.io.readAddr(1) := 1.U
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io.out := regFile.io.readData(1)
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}
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class Switch extends Module {
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val io = IO(new Bundle {
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val sw = Input(Vec(2, Bool()))
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@ -80,7 +13,7 @@ class Switch extends Module {
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io.out := io.sw(0) ^ io.sw(1)
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}
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import npc.keyboard._
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import npc.util.{PS2Port, KeyboardController, SegGenerator}
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class Keyboard extends Module {
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val io = IO(new Bundle {
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23
npc/core/src/main/scala/RegisterFile.scala
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23
npc/core/src/main/scala/RegisterFile.scala
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@ -0,0 +1,23 @@
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import chisel3._
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class RegisterFile(readPorts: Int) extends Module {
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require(readPorts >= 0)
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val io = IO(new Bundle {
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val writeEnable = Input(Bool())
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val writeAddr = Input(UInt(5.W))
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val writeData = Input(UInt(32.W))
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val readAddr = Input(Vec(readPorts, UInt(5.W)))
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val readData = Output(Vec(readPorts, UInt(32.W)))
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})
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val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W))))
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for (i <- 1 until 32) {
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regFile(i) := regFile(i)
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}
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regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr))
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regFile(0) := 0.U
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for (i <- 0 until readPorts) {
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io.readData(i) := regFile(io.readAddr(i))
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}
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}
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@ -1,35 +1,52 @@
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package npc.seg
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package npc.util
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import chisel3._
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import chisel3.util.{Decoupled}
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import chisel3.util._
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import chisel3.util.log2Ceil
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class SegInput(width: Int) extends Bundle {
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require(width > 0)
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val addr = UInt(width.W)
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val value = UInt(log2Ceil(width).W)
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}
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object SegInput {
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def apply(width: Int): SegInput = {
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return new SegInput(width)
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}
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}
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class SegGenerator(width: Int) extends {
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class SegGenerator(seg_count: Int) extends Module {
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val io = IO(new Bundle {
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val write = Flipped(Decoupled(SegInput(8)))
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val segs = Output(Vec(width, UInt(8.W)))
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val keycode = Flipped(Decoupled(UInt(8.W)))
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val segs = Output(Vec(seg_count, UInt(8.W)))
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})
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val seg_regs = RegInit(VecInit(Seq.fill(width)(0.U(8.W))))
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io.segs := seg_regs
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when(io.write.valid) {
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val data = io.write.bits
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seg_regs(data.addr) := data.value
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io.write.ready := true.B
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}.otherwise {
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io.write.ready := false.B
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io.keycode.ready := false.B
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when(io.keycode.valid) {
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io.keycode.ready := true.B
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}
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val seg_regs = RegInit(VecInit(Seq.fill(seg_count)(0.U(8.W))))
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val last_keycode = RegInit(0.U(8.W))
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val digit_to_seg = ((0 until 16).map(_.U)).zip(Seq(
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"b00000011".U, "b10011111".U, "b00100101".U, "b00001101".U,
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"b10011001".U, "b01001001".U, "b01000001".U, "b00011111".U,
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"b00000001".U, "b00001001".U, "b00010001".U, "b11000001".U,
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"b01100011".U, "b10000101".U, "b01100001".U, "b01110001".U,
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))
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val keycode_to_ascii = Seq(
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0x1C.U, 0x32.U, 0x21.U, 0x23.U, 0x24.U, 0x2B.U,
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0x34.U, 0x33.U, 0x43.U, 0x3B.U, 0x42.U, 0x4B.U,
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0x3A.U, 0x31.U, 0x44.U, 0x4D.U, 0x15.U, 0x2D.U,
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0x1B.U, 0x2C.U, 0x3C.U, 0x2A.U, 0x1D.U, 0x22.U,
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0x35.U, 0x1A.U, 0x45.U, 0x16.U, 0x1E.U, 0x26.U,
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0x25.U, 0x2E.U, 0x36.U, 0x3D.U, 0x3E.U, 0x46.U,
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).zip(((0x41 to 0x5A) ++ (0x30 to 0x39)).map(_.U))
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// val keycode = Mux(io.keycode.ready && io.keycode.valid, io.keycode.bits, keycode)
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val keycode = RegEnable(io.keycode.bits, io.keycode.ready && io.keycode.valid)
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val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4))
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val keycode_seg = keycode_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
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val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii)
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val ascii_digits = VecInit(ascii(3,0)) ++ VecInit(ascii(6,4))
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val ascii_seg = ascii_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
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val (counter, _) = Counter(io.keycode.valid && io.keycode.ready && io.keycode.bits =/= keycode, 0xFF)
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val count_digits = VecInit(counter(3,0)) ++ VecInit(counter(7,4))
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val count_seg = count_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
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seg_regs := keycode_seg ++ ascii_seg ++ count_seg ++ Seq(0xFF.U, 0xFF.U)
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io.segs := seg_regs
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}
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