diff --git a/npc/core/src/main/scala/ALU.scala b/npc/core/src/main/scala/ALU.scala
index a5cae78..70f0fea 100644
--- a/npc/core/src/main/scala/ALU.scala
+++ b/npc/core/src/main/scala/ALU.scala
@@ -9,7 +9,7 @@ class ALUControlInterface extends Bundle {
     val aOpAdd, aOpSub, aOpNot, aOpAnd, aOpOr, aOpXor, aOpSlt, aOpEq, aOpNop = Value
   }
   object SrcSelect extends ChiselEnum {
-    val aSrcRs2, aSrcImm = Value
+    val aSrcRs1, aSrcImm = Value
   }
   val op = Input(OpSelect())
   val src = Input(SrcSelect())
@@ -23,7 +23,7 @@ class ALUControlInterface extends Bundle {
 class ALU[T <: UInt](tpe: T) extends Module {
   val control = IO(new ALUControlInterface)
   val in = IO(new Bundle {
-    val a = Input(Vec(control.SrcSelect.getWidth, tpe))
+    val a = Input(Vec(control.SrcSelect.all.length, tpe))
     val b = Input(tpe)
   })
   val out = IO(new Bundle {
diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala
index 5aa3923..b523843 100644
--- a/npc/core/src/main/scala/Main.scala
+++ b/npc/core/src/main/scala/Main.scala
@@ -71,8 +71,6 @@ class Control(width: Int) extends Module {
   val reversePrefixSum = dstList.scanLeft(0)(_ + _.getWidth).reverse
   val slices = reversePrefixSum.zip(reversePrefixSum.tail)
   val srcList = slices.map(s => out(s._1 - 1, s._2))
-  // println(dstList)
-  // println(srcList)
 
   srcList
     .zip(dstList.reverse)
@@ -128,7 +126,9 @@ class Flow extends Module {
   ram.writePorts(0).data := 1.U
   ram.writePorts(0).enable := false.B
 
-  alu.in.a := reg.out.src(0)
+  import control.alu.SrcSelect._
+  alu.in.a(aSrcRs1.litValue.toInt) := reg.out.src(0)
+  alu.in.a(aSrcImm.litValue.toInt) := inst(31, 20)
   alu.in.b := reg.out.src(1)
   dontTouch(control.out)
 }