> sim RTL

ysyx_22040000 李心杨
Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux
 13:29:52  up  22:08,  2 users,  load average: 1.26, 1.02, 1.00
This commit is contained in:
tracer-ysyx 2024-01-01 13:29:52 +08:00 committed by xinyangli
parent 19e19610f8
commit e3d600fc21
5 changed files with 86 additions and 31 deletions

View file

@ -1,7 +1,6 @@
module top(
input a,
input b,
output f
input [1:0] sw,
output ledr
);
assign f = a ^ b;
assign ledr = sw[1] ^ sw[0];
endmodule