npc,refactor: remove original difftest wrapper, cleanup code

npc/core/src/main/scala/components/ALU.scala

@@ -6,7 +6,8 @@ import shapeless.{HNil, ::}
 
 class ALUControlInterface extends Bundle {
   object OpSelect extends ChiselEnum {
-    val aOpAdd, aOpSub, aOpNot, aOpAnd, aOpOr, aOpXor, aOpSlt, aOpSltu, aOpSll, aOpSrl, aOpSra = Value
+    val aOpAdd, aOpSub, aOpNot, aOpAnd, aOpOr, aOpXor, aOpSlt, aOpSltu, aOpSll,
+        aOpSrl, aOpSra = Value
   }
   object SrcASelect extends ChiselEnum {
     val aSrcARs1, aSrcAPc, aSrcAZero = Value
@@ -54,19 +55,21 @@ class ALU[T <: UInt](tpe: T) extends Module {
 
   import control.OpSelect._
 
-  out.result := MuxLookup(control.op, 0.U)(Seq(
-    aOpAdd -> add,
-    aOpSub -> sub,
-    aOpNot -> not,
-    aOpAnd -> and,
-    aOpOr  -> or,
-    aOpXor -> xor,
-    aOpSlt -> slt,
-    aOpSltu -> sltu,
-    aOpSll -> sll,
-    aOpSrl -> srl,
-    aOpSra -> sra.asUInt
-  ))
+  out.result := MuxLookup(control.op, 0.U)(
+    Seq(
+      aOpAdd -> add,
+      aOpSub -> sub,
+      aOpNot -> not,
+      aOpAnd -> and,
+      aOpOr -> or,
+      aOpXor -> xor,
+      aOpSlt -> slt,
+      aOpSltu -> sltu,
+      aOpSll -> sll,
+      aOpSrl -> srl,
+      aOpSra -> sra.asUInt
+    )
+  )
 }
 
 object ALU {

npc/core/src/main/scala/components/Mem.scala

@@ -1,13 +1,15 @@
 package flow.components
 
 import chisel3._
+import chisel3.experimental.noPrefix
 import chisel3.util.HasBlackBoxPath
 import chisel3.util.HasBlackBoxResource
 import chisel3.util.log2Ceil
-import chisel3.experimental.noPrefix
-import scala.collection.SeqMap
 import flow.components
-import shapeless.{HNil, ::}
+import shapeless.::
+import shapeless.HNil
+
+import scala.collection.SeqMap
 
 class RamControlInterface(addrWidth: Int) extends Bundle {
   val valid = Input(Bool())