npc: Register File

npc/core/src/main/scala/RegisterFile.scala

@@ -1,25 +1,73 @@
-package npc.util
+package flowpc.components
 
 import chisel3._
+import chisel3.util.log2Ceil
+import chisel3.util.UIntToOH
+import chisel3.util.MuxLookup
 
-class RegisterFile(readPorts: Int) extends Module {
-  require(readPorts >= 0)
-  val io = IO(new Bundle {
-    val writeEnable = Input(Bool())
-    val writeAddr = Input(UInt(5.W))
-    val writeData = Input(UInt(32.W))
-    val readAddr = Input(Vec(readPorts, UInt(5.W)))
-    val readData = Output(Vec(readPorts, UInt(32.W)))
-  })
+class RegControl extends Bundle {
+  val writeEnable = Input(Bool()) 
 
-  val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W))))
-  for (i <- 1 until 32) {
-    regFile(i) := regFile(i)
+  object WriteSelect extends ChiselEnum {
+    val rAluOut, rMemOut = Value
+  }
+  val writeSelect = Input(WriteSelect())
+}
+
+class RegFileData[T <: Data](size:Int, tpe: T, numReadPorts: Int, numWritePorts: Int) extends Bundle {
+  val write = new Bundle {
+    val addr = Input(UInt(size.W))
+    val data = Vec(numWritePorts, Input(tpe))
+  }
+  val read = Vec(numReadPorts, new Bundle {
+    val rs = Input(UInt(size.W))
+    val src = Output(tpe)
+  })
+}
+
+class RegFileInterface[T <: Data](size: Int, tpe: T, numReadPorts: Int, numWritePorts: Int) extends Bundle {
+  val control = new RegControl
+  val data = new RegFileData(size, tpe, numReadPorts, numWritePorts)
+}
+
+class RegisterFileCore[T <: Data](size: Int, tpe: T, numReadPorts: Int) extends Module {
+  require(numReadPorts >= 0)
+  val writePort = IO(new Bundle {
+    val enable = Input(Bool())
+    val addr = Input(UInt(log2Ceil(size).W))
+    val data = Input(tpe)
+  })
+  val readPorts = IO(Vec(numReadPorts, new Bundle {
+    val addr = Input(UInt(log2Ceil(size).W))
+    val data = Output(tpe)
+  }))
+
+  val regFile = RegInit(VecInit(Seq.fill(size)(0.U(tpe.getWidth.W))))
+  val writeAddrOH = UIntToOH(writePort.addr)
+  for ((reg, i) <- regFile.zipWithIndex.tail) {
+    reg := Mux(writeAddrOH(i) && writePort.enable, writePort.data, reg)
   }
-  regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr))
   regFile(0) := 0.U
 
-  for (i <- 0 until readPorts) {
-    io.readData(i) := regFile(io.readAddr(i))
+  for (readPort <- readPorts) {
+    readPort.data := regFile(readPort.addr)
+  }
+}
+
+object RegisterFile {
+  def apply[T <: Data](size: Int, tpe: T, numReadPorts: Int, numWritePorts: Int): RegFileInterface[T] = {
+    val core = Module(new RegisterFileCore(size, tpe, numReadPorts))
+    val _out = Wire(new RegFileInterface(size, tpe, numReadPorts, numWritePorts))
+    val clock = core.clock
+    for (i <- 0 until numReadPorts) {
+      core.readPorts(i).addr := _out.data.read(i).rs
+      _out.data.read(i).src := core.readPorts(i).data
+    }
+    core.writePort.addr := _out.data.write.addr
+    core.writePort.data := MuxLookup(_out.control.writeSelect, 0.U)(
+      _out.control.WriteSelect.all.map(x => (x -> _out.data.write.data(x.asUInt).asUInt))
+    )
+    core.writePort.enable := _out.control.writeEnable
+    _out
   }
 }