> configure(npc)

ysyx_22040000 李心杨 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux 13:51:33 up 1 day 22:38, 2 users, load average: 3.60, 1.55, 1.34
2024-01-06 13:51:33 +08:00 · 2024-01-06 13:51:33 +08:00 · b4bef0fb64
commit b4bef0fb64
parent d4ab3e5752
12 changed files with 448 additions and 16 deletions
--- a/npc/core/test_run_dir/With_32_width_add_should_work/ALUGenerator.lo.fir
+++ b/npc/core/test_run_dir/With_32_width_add_should_work/ALUGenerator.lo.fir
@ -0,0 +1,42 @@
+FIRRTL version 1.2.0
+circuit ALUGenerator :
+  module ALUGenerator :
+    input clock : Clock
+    input reset : UInt<1>
+    input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
+    output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+
+    node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
+    node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
+    node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
+    node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
+    node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
+    node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
+    node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
+    node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
+    node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
+    node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
+    node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
+    node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
+    node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
+    node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
+    io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
--- a/npc/core/test_run_dir/With_32_width_and_should_work/ALUGenerator.lo.fir
+++ b/npc/core/test_run_dir/With_32_width_and_should_work/ALUGenerator.lo.fir
@ -0,0 +1,42 @@
+FIRRTL version 1.2.0
+circuit ALUGenerator :
+  module ALUGenerator :
+    input clock : Clock
+    input reset : UInt<1>
+    input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
+    output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+
+    node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
+    node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
+    node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
+    node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
+    node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
+    node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
+    node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
+    node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
+    node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
+    node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
+    node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
+    node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
+    node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
+    node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
+    io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
--- a/npc/core/test_run_dir/With_32_width_compare_should_work/ALUGenerator.lo.fir
+++ b/npc/core/test_run_dir/With_32_width_compare_should_work/ALUGenerator.lo.fir
@ -0,0 +1,42 @@
+FIRRTL version 1.2.0
+circuit ALUGenerator :
+  module ALUGenerator :
+    input clock : Clock
+    input reset : UInt<1>
+    input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
+    output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+
+    node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
+    node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
+    node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
+    node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
+    node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
+    node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
+    node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
+    node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
+    node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
+    node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
+    node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
+    node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
+    node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
+    node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
+    io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
--- a/npc/core/test_run_dir/With_32_width_equal_should_work/ALUGenerator.lo.fir
+++ b/npc/core/test_run_dir/With_32_width_equal_should_work/ALUGenerator.lo.fir
@ -0,0 +1,42 @@
+FIRRTL version 1.2.0
+circuit ALUGenerator :
+  module ALUGenerator :
+    input clock : Clock
+    input reset : UInt<1>
+    input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
+    output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+
+    node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
+    node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
+    node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
+    node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
+    node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
+    node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
+    node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
+    node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
+    node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
+    node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
+    node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
+    node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
+    node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
+    node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
+    io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
--- a/npc/core/test_run_dir/With_32_width_not_should_work/ALUGenerator.lo.fir
+++ b/npc/core/test_run_dir/With_32_width_not_should_work/ALUGenerator.lo.fir
@ -0,0 +1,42 @@
+FIRRTL version 1.2.0
+circuit ALUGenerator :
+  module ALUGenerator :
+    input clock : Clock
+    input reset : UInt<1>
+    input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
+    output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+
+    node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
+    node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
+    node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
+    node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
+    node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
+    node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
+    node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
+    node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
+    node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
+    node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
+    node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
+    node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
+    node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
+    node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
+    io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
--- a/npc/core/test_run_dir/With_32_width_or_should_work/ALUGenerator.lo.fir
+++ b/npc/core/test_run_dir/With_32_width_or_should_work/ALUGenerator.lo.fir
@ -0,0 +1,42 @@
+FIRRTL version 1.2.0
+circuit ALUGenerator :
+  module ALUGenerator :
+    input clock : Clock
+    input reset : UInt<1>
+    input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
+    output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+
+    node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
+    node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
+    node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
+    node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
+    node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
+    node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
+    node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
+    node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
+    node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
+    node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
+    node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
+    node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
+    node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
+    node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
+    io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
--- a/npc/core/test_run_dir/With_32_width_sub_should_work/ALUGenerator.lo.fir
+++ b/npc/core/test_run_dir/With_32_width_sub_should_work/ALUGenerator.lo.fir
@ -0,0 +1,42 @@
+FIRRTL version 1.2.0
+circuit ALUGenerator :
+  module ALUGenerator :
+    input clock : Clock
+    input reset : UInt<1>
+    input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
+    output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+
+    node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
+    node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
+    node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
+    node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
+    node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
+    node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
+    node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
+    node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
+    node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
+    node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
+    node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
+    node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
+    node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
+    node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
+    io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
--- a/npc/core/test_run_dir/With_32_width_sub_should_work_with_negative_result/ALUGenerator.lo.fir
+++ b/npc/core/test_run_dir/With_32_width_sub_should_work_with_negative_result/ALUGenerator.lo.fir
@ -0,0 +1,42 @@
+FIRRTL version 1.2.0
+circuit ALUGenerator :
+  module ALUGenerator :
+    input clock : Clock
+    input reset : UInt<1>
+    input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
+    output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+
+    node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
+    node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
+    node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
+    node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
+    node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
+    node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
+    node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
+    node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
+    node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
+    node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
+    node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
+    node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
+    node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
+    node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
+    io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
--- a/npc/core/test_run_dir/With_32_width_sub_should_work_with_positive_result/ALUGenerator.lo.fir
+++ b/npc/core/test_run_dir/With_32_width_sub_should_work_with_positive_result/ALUGenerator.lo.fir
@ -0,0 +1,42 @@
+FIRRTL version 1.2.0
+circuit ALUGenerator :
+  module ALUGenerator :
+    input clock : Clock
+    input reset : UInt<1>
+    input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
+    output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+
+    node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
+    node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
+    node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
+    node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
+    node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
+    node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
+    node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
+    node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
+    node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
+    node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
+    node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
+    node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
+    node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
+    node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
+    io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
--- a/npc/core/test_run_dir/With_32_width_xor_should_work/ALUGenerator.lo.fir
+++ b/npc/core/test_run_dir/With_32_width_xor_should_work/ALUGenerator.lo.fir
@ -0,0 +1,42 @@
+FIRRTL version 1.2.0
+circuit ALUGenerator :
+  module ALUGenerator :
+    input clock : Clock
+    input reset : UInt<1>
+    input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+    input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
+    output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
+
+    node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
+    node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
+    node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
+    node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
+    node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
+    node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
+    node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
+    node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
+    node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
+    node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
+    node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
+    node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
+    node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
+    node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
+    node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
+    node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
+    io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]