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chore: clang format

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xinyangli 2024-07-22 17:45:49 +08:00
parent f5ea31f676
commit b317827c3c
Signed by: xin
SSH key fingerprint: SHA256:qZ/tzd8lYRtUFSrfBDBMcUqV4GHKxqeqRA3huItgvbk
16 changed files with 216 additions and 181 deletions
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3
npc/.gdbinit Normal file
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@ -0,0 +1,3 @@
set substitute-path /build/am-kernels /home/xin/repo/ysyx-workbench/am-kernels
file /nix/store/g8hi9rlby6xm7grzcpfc8lpmdfgv1i92-am-kernel-riscv32-none-elf-2024-07-10/libexec/am-kernels/add
target remote /tmp/gdbstub-npc.sock

2
npc/core/src/main/scala/utils/DPI.scala
View file

@ -5,7 +5,7 @@ import chisel3.util.HasBlackBoxResource
// class DiffTester extends BlackBox with HasBlackBoxResource {
// val io = IO(new Bundle {
// val regs =
// val regs =
// })
// addResource("difftest.v");
// }

4
npc/core/src/test/scala/Main.scala
View file

@ -13,7 +13,7 @@ class RV32CPUSpec extends AnyFreeSpec with ChiselScalatestTester {
import chisel3.util.{SRAM, SRAMInterface, HexMemoryFile}
class UserMem extends Module {
val io = IO(new SRAMInterface(1024, UInt(32.W), 1, 1, 0))
val memoryFile = HexMemoryFile("../resource/addi.txt")
val memoryFile = HexMemoryFile("../resource/addi.txt")
io :<>= SRAM(
size = 1024,
tpe = UInt(32.W),
@ -22,7 +22,7 @@ class RV32CPUSpec extends AnyFreeSpec with ChiselScalatestTester {
numReadwritePorts = 0,
memoryFile = memoryFile
)
val read = io.readPorts(0).data
printf(cf"memoryFile=$memoryFile, readPort=$read%x\n")
}

42
npc/csrc/Switch/main.cpp
View file

@ -1,36 +1,36 @@
#include <cstdlib>
#include <VSwitch.h>
#include <cassert>
#include <cstdlib>
#include <verilated.h>
#include <verilated_vcd_c.h>
#include <VSwitch.h>
const int MAX_SIM_TIME=100;
const int MAX_SIM_TIME = 100;
int main(int argc, char **argv, char **env) {
int sim_time = 0;
Verilated::commandArgs(argc, argv);
VSwitch *top = new VSwitch;
int sim_time = 0;
Verilated::commandArgs(argc, argv);
VSwitch *top = new VSwitch;
Verilated::traceEverOn(true);
VerilatedVcdC *m_trace = new VerilatedVcdC;
Verilated::traceEverOn(true);
VerilatedVcdC *m_trace = new VerilatedVcdC;
#ifdef VERILATOR_TRACE
top->trace(m_trace, 5);
m_trace->open("waveform.vcd");
top->trace(m_trace, 5);
m_trace->open("waveform.vcd");
#endif
for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) {
top->io_sw_0 = rand() % 2;
top->io_sw_1 = rand() % 2;
top->eval();
printf("sw0 = %d, sw1 = %d, ledr = %d\n", top->io_sw_0, top->io_sw_1, top->io_out);
assert(top->io_out == (top->io_sw_0 ^ top->io_sw_1));
for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) {
top->io_sw_0 = rand() % 2;
top->io_sw_1 = rand() % 2;
top->eval();
printf("sw0 = %d, sw1 = %d, ledr = %d\n", top->io_sw_0, top->io_sw_1,
top->io_out);
assert(top->io_out == (top->io_sw_0 ^ top->io_sw_1));
#ifdef VERILATOR_TRACE
m_trace->dump(sim_time);
m_trace->dump(sim_time);
#endif
}
}
#ifdef VERILATOR_TRACE
m_trace->close();
m_trace->close();
#endif
delete top;
exit(EXIT_SUCCESS);
delete top;
exit(EXIT_SUCCESS);
}