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> configure(npc)

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ysyx_22040000 李心杨
 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar  1 12:35:11 UTC 2024 x86_64 GNU/Linux
  15:19:20  up 3 days  6:09,  2 users,  load average: 2.75, 1.76, 1.60
This commit is contained in:
tracer-ysyx 2024-03-12 15:19:20 +08:00 • committed by xinyangli
parent 0560c97eda
commit a7d59b4d37
5 changed files with 81 additions and 35 deletions
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40
npc/core/src/test/scala/RegisterFile.scala
View file

@ -1,4 +1,4 @@
package flowpc
package flow
import chisel3._
import chiseltest._
@ -41,22 +41,40 @@ class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
}
}
"RegisterInterface" - {
"worked" in {
class Top extends Module {
val io = IO(new RegFileInterface(32, UInt(32.W), 2, 2))
val rf = RegisterFile(32, UInt(32.W), 2, 2)
io :<>= rf
}
class Top extends Module {
val io = IO(new RegFileInterface(32, UInt(32.W), 2, 2))
val rf = RegisterFile(32, UInt(32.W), 2, 2)
io :<>= rf
}
"write" in {
test(new Top).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
import c.io.control.WriteSelect._
val writePort = rAluOut.litValue.toInt
c.io.control.writeEnable.poke(true)
c.io.control.writeSelect.poke(rAluOut)
c.io.data.write.addr.poke(5)
c.io.data.write.data(writePort).poke(0xcdef)
c.io.data.read(0).rs.poke(5)
c.io.in.writeAddr.poke(5)
c.io.in.writeData(writePort).poke(0xcdef)
c.io.in.rs(0).poke(5)
c.clock.step(1)
c.io.data.read(0).src.expect(0xcdef)
c.io.out.src(0).expect(0xcdef)
}
}
"no data is written when not enabled" in {
test(new Top).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
import c.io.control.WriteSelect._
val writePort = rAluOut.litValue.toInt
c.io.control.writeEnable.poke(true)
c.io.control.writeSelect.poke(rAluOut)
c.io.in.writeAddr.poke(5)
c.io.in.writeData(writePort).poke(0xcdef)
c.io.in.rs(0).poke(5)
c.clock.step(1)
c.io.control.writeEnable.poke(false)
c.io.in.writeData(writePort).poke(0x1234)
c.clock.step(1)
c.io.out.src(0).expect(0xcdef)
}
}
}