refactor: move to dpi module for memory access

npc/core/src/main/resources/RamDpi.v

@@ -0,0 +1,24 @@
+import "DPI-C" function int pmem_read(input int addr);
+import "DPI-C" function void pmem_write(input int waddr, input int wdata, input byte wmask);
+
+module RamDpi (
+  input writeEnable,
+  input valid,
+  input [31:0] writeAddr,
+  input [31:0] writeData,
+  input [3:0] writeMask,
+  input reg [31:0] readAddr,
+  output reg [31:0] readData
+);
+  always @(*) begin
+    if (valid) begin // 有读写请求时
+      readData = pmem_read(readAddr);
+      if (writeEnable) begin // 有写请求时
+        pmem_write(writeAddr, writeData, { 4'h0, writeMask });
+      end
+    end
+    else begin
+      readData = 0;
+    end
+  end
+endmodule

npc/core/src/main/scala/FlowMain.scala

@@ -74,27 +74,18 @@ class Control(width: Int) extends Module {
     })
 }
 
-import flow.components.{RegisterFile, ProgramCounter, ALU}
+import flow.components.{RegisterFile, ProgramCounter, ALU, RamDpi}
 import chisel3.util.experimental.loadMemoryFromFileInline
 class Flow extends Module {
   val dataType = UInt(32.W)
-
-  val ram = SRAM(
-    size = 1024,
-    tpe = dataType,
-    numReadPorts = 2,
-    numWritePorts = 1,
-    numReadwritePorts = 0,
-    memoryFile = HexMemoryFile("./resource/addi.txt")
-  )
+  val ram = Module(new RamDpi)
   val control = Module(new Control(32))
   val reg = Module(new RegisterFile(dataType, 32, 2))
   val pc = Module(new ProgramCounter(dataType))
   val alu = Module(new ALU(dataType))
 
-  ram.readPorts(0).enable := true.B
-  ram.readPorts(0).address := pc.out - 0x80000000L.U
-  val inst = ram.readPorts(0).data
+  ram.io.readAddr := pc.out
+  val inst = ram.io.readData
 
   Trace.traceName(reg.control.writeEnable)
   dontTouch(reg.control.writeEnable)
@@ -111,18 +102,20 @@ class Flow extends Module {
 
   import control.reg.WriteSelect._
   reg.in.writeData(rAluOut.litValue.toInt) := alu.out.result
+
   // TODO: Read address in load command goes here
-  ram.readPorts(1).enable := false.B
-  ram.readPorts(1).address := 0.U
-  reg.in.writeData(rMemOut.litValue.toInt) := ram.readPorts(1).data
+  reg.in.writeData(rMemOut.litValue.toInt) := DontCare
+
   reg.in.writeAddr := inst(11, 7)
   reg.in.rs(0) := inst(19, 15)
   reg.in.rs(1) := inst(24, 20)
 
   // TODO: Memory write goes here
-  ram.writePorts(0).address := 1.U
-  ram.writePorts(0).data := 1.U
-  ram.writePorts(0).enable := false.B
+  ram.io.writeAddr := DontCare
+  ram.io.writeData := DontCare
+  ram.io.writeMask := DontCare
+  ram.io.writeEnable := false.B
+  ram.io.valid := true.B
 
   import control.alu.SrcSelect._
   alu.in.a(aSrcRs1.litValue.toInt) := reg.out.src(0)

npc/core/src/main/scala/Mem.scala

@@ -1 +1,24 @@
-package flow.components
+package flow.components
+
+import chisel3._
+import chisel3.util.HasBlackBoxPath
+import chisel3.util.HasBlackBoxResource
+import chisel3.util.log2Ceil
+import chisel3.experimental.noPrefix
+import scala.collection.SeqMap
+import javax.swing.plaf.synth.SynthRadioButtonMenuItemUI
+
+class RamInterface[T <: Data](tpe: T, addrWidth: Int) extends Bundle {
+  val valid = Input(Bool())
+  val writeEnable = Input(Bool())
+  val writeAddr = Input(UInt(addrWidth.W))
+  val writeData = Input(tpe)
+  val writeMask = Input(UInt((addrWidth / 8).W))
+  val readAddr = Input(UInt(addrWidth.W))
+  val readData = Output(tpe)
+}
+
+class RamDpi extends BlackBox with HasBlackBoxResource {
+  val io = IO(new RamInterface(UInt(32.W), 32))
+  addResource("/RamDpi.v")
+}

npc/core/src/main/scala/RegisterFile.scala

@@ -12,7 +12,7 @@ class RegControl extends Bundle {
     val rAluOut, rMemOut = Value
   }
 
-  val writeEnable = Input(Bool()) 
+  val writeEnable = Input(Bool())
   val writeSelect = Input(WriteSelect())
 
   type CtrlTypes = Bool :: WriteSelect.Type :: HNil
@@ -25,7 +25,7 @@ class RegControl extends Bundle {
 class RegisterFile[T <: Data](tpe: T, regCount: Int, numReadPorts: Int) extends Module {
   require(numReadPorts >= 0)
   val control = IO(new RegControl)
-  val dataAddrWidth = log2Ceil(tpe.getWidth).W
+  val dataAddrWidth = log2Ceil(regCount).W
   val in = IO(new Bundle {
     val writeAddr = Input(UInt(dataAddrWidth))
     val writeData = Input(Vec(control.WriteSelect.all.length, tpe))