nemu: support yield()

abstract-machine/am/include/arch/riscv.h

@@ -1,5 +1,6 @@
 #ifndef ARCH_H__
 #define ARCH_H__
+#include <stdint.h>
 
 #ifdef __riscv_e
 #define NR_REGS 16
@@ -9,10 +10,13 @@
 
 struct Context {
   // TODO: fix the order of these members to match trap.S
-  uintptr_t mepc, mcause, gpr[NR_REGS], mstatus;
+  uintptr_t gpr[NR_REGS];
+  uintptr_t mcause, mstatus, mepc;
   void *pdir;
 };
 
+enum Cause { CauseEnvironmentCallFromMMode = 11 };
+
 #ifdef __riscv_e
 #define GPR1 gpr[15] // a5
 #else

abstract-machine/am/src/platform/nemu/trm.c

@@ -6,7 +6,7 @@ int main(const char *args);
 
 Area heap = RANGE(&_heap_start, PMEM_END);
 #ifndef MAINARGS
-#define MAINARGS "5"
+#define MAINARGS "i"
 #endif
 static const char mainargs[] = MAINARGS;
 

abstract-machine/am/src/riscv/nemu/cte.c

@@ -1,14 +1,20 @@
+#include "arch/riscv.h"
 #include <am.h>
-#include <riscv/riscv.h>
 #include <klib.h>
+#include <riscv/riscv.h>
 
-static Context* (*user_handler)(Event, Context*) = NULL;
+static Context *(*user_handler)(Event, Context *) = NULL;
 
-Context* __am_irq_handle(Context *c) {
+Context *__am_irq_handle(Context *c) {
   if (user_handler) {
     Event ev = {0};
     switch (c->mcause) {
-      default: ev.event = EVENT_ERROR; break;
+    case CauseEnvironmentCallFromMMode:
+      ev.event = EVENT_YIELD;
+      break;
+    default:
+      ev.event = EVENT_ERROR;
+      break;
     }
 
     c = user_handler(ev, c);
@@ -20,7 +26,7 @@ Context* __am_irq_handle(Context *c) {
 
 extern void __am_asm_trap(void);
 
-bool cte_init(Context*(*handler)(Event, Context*)) {
+bool cte_init(Context *(*handler)(Event, Context *)) {
   // initialize exception entry
   asm volatile("csrw mtvec, %0" : : "r"(__am_asm_trap));
 
@@ -42,9 +48,6 @@ void yield() {
 #endif
 }
 
-bool ienabled() {
-  return false;
-}
+bool ienabled() { return false; }
 
-void iset(bool enable) {
-}
+void iset(bool enable) {}