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> configure(npc)

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ysyx_22040000 李心杨
 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar  1 12:35:11 UTC 2024 x86_64 GNU/Linux
  23:25:23  up 2 days 14:15,  2 users,  load average: 0.55, 0.82, 0.95
This commit is contained in:
tracer-ysyx 2024-03-11 23:25:23 +08:00 • committed by xinyangli
parent ee22c1541d
commit 8fc1f3838b
9 changed files with 155 additions and 90 deletions
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29
npc/core/src/test/scala/RegisterFile.scala
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@ -5,8 +5,6 @@ import chiseltest._
import org.scalatest.freespec.AnyFreeSpec
import chiseltest.simulator.WriteVcdAnnotation
import chisel3.util.{SRAM}
import flowpc.components._
class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
"RegisterFileCore" - {
@ -43,19 +41,22 @@ class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
}
}
"RegisterInterface" - {
class Top extends Module {
val io = RegisterFile(32, UInt(32.W), 2, 2)
}
"worked" in {
test(new Top) { c =>
// import c.io.control.WriteSelect._
// c.io.control.writeEnable.poke(true)
// c.io.control.writeSelect.poke(rAluOut)
// c.io.data.write.addr.poke(1)
// c.io.data.write.data(rAluOut.asUInt).poke(0xcdef)
// c.io.data.read(0).rs.poke(1)
// c.clock.step(1)
// c.io.data.read(0).src.expect(0xcdef)
class Top extends Module {
val io = IO(new RegFileInterface(32, UInt(32.W), 2, 2))
val rf = RegisterFile(32, UInt(32.W), 2, 2)
io :<>= rf
}
test(new Top).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
import c.io.control.WriteSelect._
val writePort = rAluOut.litValue.toInt
c.io.control.writeEnable.poke(true)
c.io.control.writeSelect.poke(rAluOut)
c.io.data.write.addr.poke(5)
c.io.data.write.data(writePort).poke(0xcdef)
c.io.data.read(0).rs.poke(5)
c.clock.step(1)
c.io.data.read(0).src.expect(0xcdef)
}
}
}