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> nvboard

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ysyx_22040000 李心杨
Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux
 17:23:05  up   2:09,  2 users,  load average: 2.15, 1.50, 1.16
This commit is contained in:
tracer-ysyx 2024-01-04 17:23:05 +08:00 • committed by xinyangli
parent 5feabac34d
commit 8dfae1f22d
6 changed files with 70 additions and 40 deletions
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1
npc/.envrc Normal file
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@ -0,0 +1 @@
use flake

11
npc/.gitignore vendored
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@ -1,6 +1,3 @@
*.*
*
!*/
!Makefile !Makefile
!*.mk !*.mk
!*.[cSh] !*.[cSh]
@ -13,6 +10,14 @@ build/
*.class *.class
*.log *.log
.cache/
.bsp/
.bloop/
.metals/
# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml # virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
hs_err_pid* hs_err_pid*
.vscode/
.direnv/
compile_commands.json

2
npc/.scalafmt.conf Normal file
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@ -0,0 +1,2 @@
version = "3.7.15"
runner.dialect = scala213

66
npc/Makefile
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@ -1,42 +1,70 @@
NVBOARD_HOME ?= $(abspath ../nvboard) NVBOARD_HOME ?= $(abspath ../nvboard)
PREFIX ?= build PREFIX ?= build
OBJDIR := $(PREFIX)/obj OBJDIR := $(PREFIX)/obj
TARGET := $(OBJDIR)/Vexample CHISEL_VDIR := $(PREFIX)/chisel
VSRC := $(wildcard vsrc/*.v)
CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp)) CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
SUBMAKE := $(OBJDIR)/Vexample.mk SUBMAKE = $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
VERILATOR_FLAGS := --cc --exe VERILATOR_FLAGS := --cc --exe
LDFLAGS += $(shell sdl2-config --libs) -lSDL2_image LDFLAGS += $(shell sdl2-config --libs) -lSDL2_image
CHISEL_TOP_PACKAGE := learning
CHISEL_TOP_MODULE := Main
CHISEL_TARGET := verilog
# Pretty printing
MAKEFLAGS += --no-print-directory
GREEN=\e[32m
NC=\e[0m
define colorize
printf '$(GREEN)'$(1)'$(NC) $(2)\n'
endef
all: sim-bin nvboard-bin all: sim-bin nvboard-bin
$(OBJDIR)/Vexample: $(SUBMAKE) $(OBJDIR)/V$(CHISEL_TOP_MODULE): $(SUBMAKE)
$(MAKE) -C $(OBJDIR) -f $(notdir $(SUBMAKE)) Vexample @$(call colorize,"SUBMAKE",$^)
$(MAKE) -s -C $(OBJDIR) -f $(notdir $(SUBMAKE)) V$(CHISEL_TOP_MODULE)
$(SUBMAKE): $(VSRC) $(CPPSRCS) $(OBJDIR) $(SUBMAKE): $(CPPSRCS) $(OBJDIR) chisel-src
verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(VSRC) $(CPPSRCS) @$(call colorize,"VERILATOR",$^)
verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(CHISEL_VSRC) $(CPPSRCS)
$(OBJDIR): $(OBJDIR):
mkdir -p $(OBJDIR) mkdir -p $(OBJDIR)
sim-bin: VERILATOR_FLAGS += --trace $(CHISEL_VDIR)/filelist.f: $(wildcard src/main/scala/*.scala)
sim-bin: $(VSRC) $(CPPSRCS) $(OBJDIR)/Vexample @$(call colorize,"CIRCT",$^)
sbt --error "runMain circt.stage.ChiselMain --module $(CHISEL_TOP_PACKAGE).$(CHISEL_TOP_MODULE) --split-verilog --target $(CHISEL_TARGET) -td $(CHISEL_VDIR)"
SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp) SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp)
NXDC_FILES := $(abspath constr/top.nxdc) NXDC_FILES := $(abspath constr/top.nxdc)
$(SRC_AUTO_BIND): $(NXDC_FILES) $(SRC_AUTO_BIND): $(NXDC_FILES)
NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@ NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@
compile_commands.json: clean
$(MAKE) $(CHISEL_VDIR)/filelist.f
$(RM) compile_commands.json
bear --append -- $(MAKE) nvboard-bin
bear --append -- $(MAKE) sim-bin
.PHONY: clean nvboard sim nvboard-bin sim-bin git_trace_sim git_trace_nvboard
sim-bin: VERILATOR_FLAGS += --trace
sim-bin: $(CPPSRCS) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
nvboard-bin: OBJDIR := $(PREFIX)/nvobj nvboard-bin: OBJDIR := $(PREFIX)/nvobj
nvboard-bin: SUBMAKE := $(OBJDIR)/Vexample.mk nvboard-bin: SUBMAKE := $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
# TODO: fix this awkward way to find nvboard.a # TODO: fix this awkward way to find nvboard.a
nvboard-bin: CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a nvboard-bin: CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a
nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags) -g nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags) -g
nvboard-bin: $(VSRC) $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/Vexample nvboard-bin: $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
chisel-src: $(CHISEL_VDIR)/filelist.f
$(eval CHISEL_VSRC := $(wildcard $(CHISEL_VDIR)/*.sv))
@echo "GENERATED: $(CHISEL_VSRC)"
ifneq (,$(wildcard ../Makefile)) ifneq (,$(wildcard ../Makefile))
include ../Makefile include ../Makefile
@ -51,22 +79,16 @@ git_trace_sim:
git_trace_nvboard: git_trace_nvboard:
$(call git_commit, "nvboard") $(call git_commit, "nvboard")
.PHONY: clean nvboard sim compile_commands.json
nvboard: OBJDIR := $(PREFIX)/nvobj nvboard: OBJDIR := $(PREFIX)/nvobj
nvboard: nvboard-bin git_trace_nvboard nvboard: nvboard-bin git_trace_nvboard
@NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/Vexample @NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
sim: sim-bin git_trace_sim sim: sim-bin git_trace_sim
@echo "Running" $(OBJDIR)/Vexample "..." @echo "Running verilator sim ..."
@echo "================================" @echo "================================"
@$(OBJDIR)/Vexample @$(OBJDIR)/V$(CHISEL_TOP_MODULE)
compile_commands.json: clean
bear --output nvboard.json -- $(MAKE) nvboard-bin
bear --output all.json -- $(MAKE) sim-bin
jq -s ".[0] + .[1]" all.json nvboard.json > compile_commands.json
$(RM) all.json nvboard.json
clean: clean:
$(RM) -r $(PREFIX) $(RM) -r $(PREFIX)
$(V).SILENT:

24
npc/csrc/main.cpp
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@ -3,14 +3,14 @@
#include <cstdlib> #include <cstdlib>
#include <verilated.h> #include <verilated.h>
#include <verilated_vcd_c.h> #include <verilated_vcd_c.h>
#include <Vexample.h> #include <VMain.h>
const int MAX_SIM_TIME=100; const int MAX_SIM_TIME=100;
int main(int argc, char **argv, char **env) { int main(int argc, char **argv, char **env) {
int sim_time = 0; int sim_time = 0;
Verilated::commandArgs(argc, argv); Verilated::commandArgs(argc, argv);
Vexample *top = new Vexample; VMain *top = new VMain;
Verilated::traceEverOn(true); Verilated::traceEverOn(true);
VerilatedVcdC *m_trace = new VerilatedVcdC; VerilatedVcdC *m_trace = new VerilatedVcdC;
@ -18,16 +18,16 @@ int main(int argc, char **argv, char **env) {
top->trace(m_trace, 5); top->trace(m_trace, 5);
m_trace->open("waveform.vcd"); m_trace->open("waveform.vcd");
#endif #endif
for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) { // for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) {
CData sw = rand() & 0b11; // CData sw = rand() & 0b11;
top->sw = sw; // top->sw = sw;
top->eval(); // top->eval();
printf("sw0 = %d, sw1 = %d, ledr = %d\n", sw & 0b1, sw >> 1, top->ledr); // printf("sw0 = %d, sw1 = %d, ledr = %d\n", sw & 0b1, sw >> 1, top->ledr);
assert(top->ledr == ((sw >> 1) ^ (sw & 0b1)) ); // assert(top->ledr == ((sw >> 1) ^ (sw & 0b1)) );
#ifdef VERILATOR_TRACE // #ifdef VERILATOR_TRACE
m_trace->dump(sim_time); // m_trace->dump(sim_time);
#endif // #endif
} // }
#ifdef VERILATOR_TRACE #ifdef VERILATOR_TRACE
m_trace->close(); m_trace->close();
#endif #endif

6
npc/csrc_nvboard/main.cpp
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@ -3,15 +3,15 @@
#include <cstdlib> #include <cstdlib>
#include <verilated.h> #include <verilated.h>
#include <verilated_vcd_c.h> #include <verilated_vcd_c.h>
#include <Vexample.h> #include <VMain.h>
#include <nvboard.h> #include <nvboard.h>
const int MAX_SIM_TIME=100; const int MAX_SIM_TIME=100;
void nvboard_bind_all_pins(Vexample* top); void nvboard_bind_all_pins(VMain* top);
int main(int argc, char **argv, char **env) { int main(int argc, char **argv, char **env) {
Vexample *top = new Vexample; VMain* top = new VMain;
nvboard_bind_all_pins(top); nvboard_bind_all_pins(top);
nvboard_init(); nvboard_init();