From 8a58dfc68ad5cd2a342acf475de573554d8ead6a Mon Sep 17 00:00:00 2001
From: tracer-ysyx <tracer@ysyx.org>
Date: Tue, 26 Mar 2024 11:25:20 +0800
Subject: [PATCH] =?UTF-8?q?>=20compile=20NEMU=20ysyx=5F22040000=20?=
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 =?UTF-8?q?OS=20SMP=20PREEMPT=5FDYNAMIC=20Fri=20Mar=20=201=2012:35:11=20UT?=
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---
 nemu/.result.tmp                   | 0
 npc/core/src/main/scala/Main.scala | 6 ++++--
 2 files changed, 4 insertions(+), 2 deletions(-)
 create mode 100644 nemu/.result.tmp

diff --git a/nemu/.result.tmp b/nemu/.result.tmp
new file mode 100644
index 0000000..e69de29
diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala
index d4f38ec..95b9e61 100644
--- a/npc/core/src/main/scala/Main.scala
+++ b/npc/core/src/main/scala/Main.scala
@@ -4,8 +4,7 @@ import chisel3._
 import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
 import chisel3.util.{SRAM}
 import chisel3.stage.ChiselOption
-import npc.util.KeyboardSegController
-import flowpc.components.RegisterFile
+import npc.util.{ KeyboardSegController, RegisterFile }
 import flowpc.components.ProgramCounter
 
 class Switch extends Module {
@@ -34,9 +33,12 @@ class Keyboard extends Module {
   io.segs := seg_handler.io.segs
 }
 
+<<<<<<< Updated upstream
+=======
 class Flowpc extends Module {
   val io = IO(new Bundle { })
   val register_file = new RegisterFile(readPorts = 2);
   val pc = new ProgramCounter(32);
   val adder = new SRAM()
 }
+>>>>>>> Stashed changes