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feat: difftest framework

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This commit is contained in:
xinyangli 2024-04-05 00:16:58 +08:00
parent 97cf418c86
commit 849f2bb5f3
Signed by: xin
SSH key fingerprint: SHA256:qZ/tzd8lYRtUFSrfBDBMcUqV4GHKxqeqRA3huItgvbk
15 changed files with 318 additions and 84 deletions
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4
npc/core/src/main/scala/ALU.scala
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@ -9,7 +9,7 @@ class ALUControlInterface extends Bundle {
val aOpAdd, aOpSub, aOpNot, aOpAnd, aOpOr, aOpXor, aOpSlt, aOpEq, aOpNop = Value
}
object SrcSelect extends ChiselEnum {
val aSrcRs1, aSrcImm = Value
val aSrcRs2, aSrcImm = Value
}
val op = Input(OpSelect())
val src = Input(SrcSelect())
@ -33,7 +33,7 @@ class ALU[T <: UInt](tpe: T) extends Module {
val a = in.a(control.src.asUInt)
// val adder_b = (Fill(tpe.getWidth, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub
val add = a + in.b
val add = a + in.b
val sub = a - in.b
val and = a & in.b
val not = ~a

11
npc/core/src/main/scala/FlowMain.scala
View file

@ -87,7 +87,6 @@ class Flow extends Module {
ram.io.readAddr := pc.out
val inst = ram.io.readData
Trace.traceName(reg.control.writeEnable)
dontTouch(reg.control.writeEnable)
import control.pc.SrcSelect._
@ -107,8 +106,8 @@ class Flow extends Module {
reg.in.writeData(rMemOut.litValue.toInt) := DontCare
reg.in.writeAddr := inst(11, 7)
reg.in.rs(0) := inst(19, 15)
reg.in.rs(1) := inst(24, 20)
reg.in.rs(0) := inst(19, 15) // rs1
reg.in.rs(1) := inst(24, 20) // rs2
// TODO: Memory write goes here
ram.io.writeAddr := DontCare
@ -118,10 +117,10 @@ class Flow extends Module {
ram.io.valid := true.B
import control.alu.SrcSelect._
alu.in.a(aSrcRs1.litValue.toInt) := reg.out.src(0)
alu.in.a(aSrcRs2.litValue.toInt) := reg.out.src(1)
alu.in.a(aSrcImm.litValue.toInt) := inst(31, 20)
alu.in.b := reg.out.src(1)
alu.in.b := reg.out.src(0)
Trace.traceName(pc.out);
dontTouch(control.out)
}