From 70168608dddc66efabb627a21693a27ce2c792a8 Mon Sep 17 00:00:00 2001 From: tracer-ysyx Date: Sat, 6 Jan 2024 13:17:13 +0800 Subject: [PATCH] =?UTF-8?q?>=20configure(npc)=20=20ysyx=5F22040000=20?= =?UTF-8?q?=E6=9D=8E=E5=BF=83=E6=9D=A8=20=20Linux=20calcite=206.1.69=20#1-?= =?UTF-8?q?NixOS=20SMP=20PREEMPT=5FDYNAMIC=20Wed=20Dec=2020=2016:00:29=20U?= =?UTF-8?q?TC=202023=20x86=5F64=20GNU/Linux=20=20=2013:17:13=20=20up=201?= =?UTF-8?q?=20day=2022:03,=20=202=20users,=20=20load=20average:=201.36,=20?= =?UTF-8?q?2.08,=201.73?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- npc/core/src/main/scala/Main.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala index a27983e..9443937 100644 --- a/npc/core/src/main/scala/Main.scala +++ b/npc/core/src/main/scala/Main.scala @@ -1,6 +1,7 @@ package npc import chisel3._ +import chisel3.utils.{MuxLookup} import chisel3.stage.ChiselOption class RegisterFile(readPorts: Int) extends Module { @@ -34,7 +35,7 @@ class ALUGenerator(width: Int) extends Module { val out = Output(UInt(width.W)) }) - val adder_b = fill(width)(io.op(0)) ^ io.b // take (-b) if sub + val adder_b = Fill(width)(io.op(0)) ^ io.b // take (-b) if sub val add = io.a + adder_b val and = io.a & io.b val not = ~io.a