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12 changed files with 423 additions and 157 deletions
106
npc/core/src/main/scala/components/RV32Inst.scala
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106
npc/core/src/main/scala/components/RV32Inst.scala
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@ -0,0 +1,106 @@
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package flow.components
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import chisel3.util.BitPat
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object RV32Inst {
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private val bp = BitPat
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// format: off
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val lui = this.bp("b???????_?????_?????_???_?????_01101_11")
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val auipc = this.bp("b???????_?????_?????_???_?????_00101_11")
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val jal = this.bp("b???????_?????_?????_???_?????_11011_11")
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val jalr = this.bp("b???????_?????_?????_???_?????_11001_11")
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val beq = this.bp("b???????_?????_?????_000_?????_11000_11")
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val bne = this.bp("b???????_?????_?????_001_?????_11000_11")
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val blt = this.bp("b???????_?????_?????_100_?????_11000_11")
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val bge = this.bp("b???????_?????_?????_101_?????_11000_11")
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val bltu = this.bp("b???????_?????_?????_110_?????_11000_11")
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val bgeu = this.bp("b???????_?????_?????_111_?????_11000_11")
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val lb = this.bp("b???????_?????_?????_000_?????_00000_11")
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val lh = this.bp("b???????_?????_?????_001_?????_00000_11")
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val lw = this.bp("b???????_?????_?????_010_?????_00000_11")
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val lbu = this.bp("b???????_?????_?????_100_?????_00000_11")
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val lhu = this.bp("b???????_?????_?????_101_?????_00000_11")
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val sb = this.bp("b???????_?????_?????_000_?????_01000_11")
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val sh = this.bp("b???????_?????_?????_001_?????_01000_11")
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val sw = this.bp("b???????_?????_?????_010_?????_01000_11")
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val addi = this.bp("b???????_?????_?????_000_?????_00100_11")
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val slti = this.bp("b???????_?????_?????_010_?????_00100_11")
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val sltiu = this.bp("b???????_?????_?????_011_?????_00100_11")
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val xori = this.bp("b???????_?????_?????_100_?????_00100_11")
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val ori = this.bp("b???????_?????_?????_110_?????_00100_11")
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val andi = this.bp("b???????_?????_?????_111_?????_00100_11")
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val slli = this.bp("b0000000_?????_?????_001_?????_00100_11")
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val srli = this.bp("b0000000_?????_?????_101_?????_00100_11")
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val srai = this.bp("b0100000_?????_?????_101_?????_00100_11")
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val add = this.bp("b0000000_?????_?????_000_?????_01100_11")
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val sub = this.bp("b0100000_?????_?????_000_?????_01100_11")
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val sll = this.bp("b0000000_?????_?????_001_?????_01100_11")
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val slt = this.bp("b0000000_?????_?????_010_?????_01100_11")
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val sltu = this.bp("b0000000_?????_?????_011_?????_01100_11")
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val xor = this.bp("b0000000_?????_?????_100_?????_01100_11")
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val srl = this.bp("b0000000_?????_?????_101_?????_01100_11")
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val sra = this.bp("b0100000_?????_?????_101_?????_01100_11")
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val or = this.bp("b0000000_?????_?????_110_?????_01100_11")
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val and = this.bp("b0000000_?????_?????_111_?????_01100_11")
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val ebreak = this.bp("b0000000_00001_00000_000_00000_11100_11")
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val csrrw = this.bp("b???????_?????_?????_001_?????_11100_11")
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val mul = this.bp("b0000001_?????_?????_000_?????_01100_11")
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val mulh = this.bp("b0000001_?????_?????_001_?????_01100_11")
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val mulhsu = this.bp("b0000001_?????_?????_010_?????_01100_11")
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val mulhu = this.bp("b0000001_?????_?????_011_?????_01100_11")
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val div = this.bp("b0000001_?????_?????_100_?????_01100_11")
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val divu = this.bp("b0000001_?????_?????_101_?????_01100_11")
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val rem = this.bp("b0000001_?????_?????_110_?????_01100_11")
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val remu = this.bp("b0000001_?????_?????_111_?????_01100_11")
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val inv = this.bp("b???????_?????_?????_???_?????_?????_??")
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// format: on
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}
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import chisel3._
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import chisel3.util._
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import flow.Params
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object RV32InstSubfields {
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implicit class ImmDecoder(val inst: UInt) extends AnyVal {
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def immB: UInt = Cat(
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Fill(20, inst(31)),
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inst(7),
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inst(30, 25),
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inst(11, 8),
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0.U(1.W)
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)
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def immI: UInt = Cat(Fill(20, inst(31)), inst(31, 20))
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def immJ: UInt = Cat(
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Fill(12, inst(31)),
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inst(19, 12),
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inst(20),
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inst(30, 25),
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inst(24, 21),
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0.U(1.W)
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)
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def immS: UInt = Cat(
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Fill(20, inst(31)),
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inst(31),
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inst(30, 25),
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inst(11, 8),
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inst(7)
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)
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def immU: UInt = Cat(inst(31, 12), 0.U(12.W))
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def rd: UInt = inst(11, 7)
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def rs1: UInt = inst(19, 15)
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def rs2: UInt = inst(24, 20)
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}
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}
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@ -18,5 +18,6 @@ import io.circe.generic.JsonCodec
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import chisel3._
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case class Params(
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XLEN: Width,
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arch: String,
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csrAddrWidth: Width = 12.W
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)
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@ -14,67 +14,8 @@ import chisel3.experimental.Trace
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import scala.collection.IndexedSeqView
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import shapeless.Poly1
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import flow.components.RamControlInterface
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object RV32Inst {
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private val bp = BitPat
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// format: off
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val lui = this.bp("b???????_?????_?????_???_?????_01101_11")
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val auipc = this.bp("b???????_?????_?????_???_?????_00101_11")
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val jal = this.bp("b???????_?????_?????_???_?????_11011_11")
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val jalr = this.bp("b???????_?????_?????_???_?????_11001_11")
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val beq = this.bp("b???????_?????_?????_000_?????_11000_11")
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val bne = this.bp("b???????_?????_?????_001_?????_11000_11")
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val blt = this.bp("b???????_?????_?????_100_?????_11000_11")
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val bge = this.bp("b???????_?????_?????_101_?????_11000_11")
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val bltu = this.bp("b???????_?????_?????_110_?????_11000_11")
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val bgeu = this.bp("b???????_?????_?????_111_?????_11000_11")
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val lb = this.bp("b???????_?????_?????_000_?????_00000_11")
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val lh = this.bp("b???????_?????_?????_001_?????_00000_11")
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val lw = this.bp("b???????_?????_?????_010_?????_00000_11")
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val lbu = this.bp("b???????_?????_?????_100_?????_00000_11")
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val lhu = this.bp("b???????_?????_?????_101_?????_00000_11")
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val sb = this.bp("b???????_?????_?????_000_?????_01000_11")
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val sh = this.bp("b???????_?????_?????_001_?????_01000_11")
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val sw = this.bp("b???????_?????_?????_010_?????_01000_11")
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val addi = this.bp("b???????_?????_?????_000_?????_00100_11")
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val slti = this.bp("b???????_?????_?????_010_?????_00100_11")
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val sltiu = this.bp("b???????_?????_?????_011_?????_00100_11")
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val xori = this.bp("b???????_?????_?????_100_?????_00100_11")
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val ori = this.bp("b???????_?????_?????_110_?????_00100_11")
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val andi = this.bp("b???????_?????_?????_111_?????_00100_11")
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val slli = this.bp("b0000000_?????_?????_001_?????_00100_11")
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val srli = this.bp("b0000000_?????_?????_101_?????_00100_11")
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val srai = this.bp("b0100000_?????_?????_101_?????_00100_11")
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val add = this.bp("b0000000_?????_?????_000_?????_01100_11")
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val sub = this.bp("b0100000_?????_?????_000_?????_01100_11")
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val sll = this.bp("b0000000_?????_?????_001_?????_01100_11")
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val slt = this.bp("b0000000_?????_?????_010_?????_01100_11")
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val sltu = this.bp("b0000000_?????_?????_011_?????_01100_11")
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val xor = this.bp("b0000000_?????_?????_100_?????_01100_11")
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val srl = this.bp("b0000000_?????_?????_101_?????_01100_11")
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val sra = this.bp("b0100000_?????_?????_101_?????_01100_11")
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val or = this.bp("b0000000_?????_?????_110_?????_01100_11")
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val and = this.bp("b0000000_?????_?????_111_?????_01100_11")
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val ebreak = this.bp("b0000000_00001_00000_000_00000_11100_11")
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val mul = this.bp("b0000001_?????_?????_000_?????_01100_11")
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val mulh = this.bp("b0000001_?????_?????_001_?????_01100_11")
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val mulhsu = this.bp("b0000001_?????_?????_010_?????_01100_11")
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val mulhu = this.bp("b0000001_?????_?????_011_?????_01100_11")
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val div = this.bp("b0000001_?????_?????_100_?????_01100_11")
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val divu = this.bp("b0000001_?????_?????_101_?????_01100_11")
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val rem = this.bp("b0000001_?????_?????_110_?????_01100_11")
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val remu = this.bp("b0000001_?????_?????_111_?????_01100_11")
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val inv = this.bp("b???????_?????_?????_???_?????_?????_??")
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// format: on
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}
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import flow.components.RV32Inst
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import flow.components.RV32InstSubfields._
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import flow.components.{RegControl, PcControlInterface, ALUControlInterface}
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class Control(width: Int) extends RawModule {
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@ -447,13 +388,7 @@ class Flow extends Module {
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val npc = Wire(dataType)
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npc := pc.out + 4.U
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pc.in.exeOut := alu.out.result
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pc.in.immB := Cat(
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Fill(20, inst(31)),
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inst(7),
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inst(30, 25),
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inst(11, 8),
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0.U(1.W)
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)
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pc.in.immB := inst.immB
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control.inst := inst
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reg.control <> control.reg
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@ -499,9 +434,9 @@ class Flow extends Module {
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// printf(cf"maskedData = ${maskedData}, writeData = ${reg.in.writeData(lit(rMemOut))}\n")
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reg.in.writeData(lit(rNpc)) := npc
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reg.in.writeAddr := inst(11, 7)
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reg.in.rs(0) := inst(19, 15) // rs1
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reg.in.rs(1) := inst(24, 20) // rs2
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reg.in.writeAddr := inst.rd
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reg.in.rs(0) := inst.rs1
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reg.in.rs(1) := inst.rs2
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// TODO: Bulk connection here
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ram.io.clock := clock
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@ -521,23 +456,10 @@ class Flow extends Module {
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alu.in.b(lit(aSrcBRs2)) := reg.out.src(1)
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// alu.in.b(lit(aSrcBImmI)) := inst(31, 20).pad(aSrcBImmI.getWidth)
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alu.in.b(lit(aSrcBImmI)) := Cat(Fill(20, inst(31)), inst(31, 20))
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alu.in.b(lit(aSrcBImmJ)) := Cat(
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Fill(12, inst(31)),
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inst(19, 12),
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inst(20),
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inst(30, 25),
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inst(24, 21),
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0.U(1.W)
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)
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alu.in.b(lit(aSrcBImmS)) := Cat(
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Fill(20, inst(31)),
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inst(31),
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inst(30, 25),
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inst(11, 8),
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inst(7)
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)
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alu.in.b(lit(aSrcBImmU)) := Cat(inst(31, 12), 0.U(12.W))
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alu.in.b(lit(aSrcBImmI)) := inst.immI
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alu.in.b(lit(aSrcBImmJ)) := inst.immJ
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alu.in.b(lit(aSrcBImmS)) := inst.immS
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alu.in.b(lit(aSrcBImmU)) := inst.immU
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Trace.traceName(pc.out)
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dontTouch(control.out)
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