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ysyx_22040000 李心杨
 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar  1 12:35:11 UTC 2024 x86_64 GNU/Linux
  13:31:24  up   3:07,  2 users,  load average: 2.36, 1.52, 1.18
This commit is contained in:
tracer-ysyx 2024-03-13 13:31:24 +08:00 • committed by xinyangli
parent 3fc7b061a9
commit 545c64c479
3 changed files with 28 additions and 25 deletions
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20
npc/core/src/main/scala/Main.scala
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@ -40,6 +40,11 @@ class Control(width: Int) extends Module {
type T =
Bool :: reg.WriteSelect.Type :: pc.SrcSelect.Type :: alu.OpSelect.Type :: alu.SrcSelect.Type :: HNil
val dst: T = reg.ctrlBindPorts ++ pc.ctrlBindPorts ++ alu.ctrlBindPorts
val dstList = dst.toList
val reversePrefixSum = dstList.scanLeft(0)(_ + _.getWidth).reverse
val slices = reversePrefixSum.zip(reversePrefixSum.tail)
import reg.WriteSelect._
import pc.SrcSelect._
import alu.OpSelect._
@ -50,26 +55,15 @@ class Control(width: Int) extends Module {
// writeEnable :: writeSelect :: srcSelect ::
(addi, true.B :: rAluOut :: pStaticNpc :: aOpAdd :: aSrcImm :: HNil),
)
val default = BitPat.dontCare(dstList.map(_.getWidth).reduce(_ + _))
def toBits(t: T): BitPat = {
val list: List[Data] = t.toList
list.map(x => BitPat(x.litValue.toInt.U(x.getWidth.W))).reduceLeft(_ ## _)
}
val default = BitPat("b????????")
reg.writeEnable := false.B
reg.writeSelect := reg.WriteSelect(0.U)
alu.op := alu.OpSelect(0.U)
pc.srcSelect := pc.SrcSelect(0.U)
val out = decoder(
inst,
TruthTable(ControlMapping.map(it => (it._1 -> toBits(it._2))), default))
println(out)
val dstList = dst.toList
val reversePrefixSum = dstList.scanLeft(0)(_ + _.getWidth).reverse
val slices = reversePrefixSum.zip(reversePrefixSum.tail)
val srcList = slices.map(s => out(s._1 - 1, s._2))
srcList