> configure(npc)

ysyx_22040000 李心杨
 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux
  20:30:51  up 1 day 19:31,  2 users,  load average: 0.75, 0.84, 0.73

npc/core/src/main/scala/Keyboard.scala

@@ -0,0 +1,110 @@
+package npc.keyboard
+
+import chisel3._
+import chisel3.util.{Counter, Decoupled, Queue, Reverse, MuxLookup}
+
+import npc.seg._
+
+class PS2Port extends Bundle {
+  val clk = Input(Bool())
+  val data = Input(UInt(1.W))
+}
+
+object PS2Port {
+  def apply(): PS2Port = {
+    new PS2Port
+  }
+}
+
+class KeyboardController extends Module {
+  val io = IO(new Bundle {
+    val ps2 = PS2Port()
+    val out = Decoupled(UInt(8.W))
+  })
+  // valid only on the clock negedge of ps2_clk
+  val ps2_clk_valid = RegNext(io.ps2.clk, false.B) & ~io.ps2.clk
+  val cycle_counter = Counter(11)
+  val concated_data = RegInit(0.U(8.W))
+
+  val queue_io = Wire(Flipped(Decoupled(UInt(8.W))))
+  val queue = Queue(queue_io, entries = 8)
+  val received = RegInit(Bool(), false.B)
+  val pushed = RegNext(queue_io.valid && queue_io.ready, false.B)
+  queue_io.valid := false.B
+  queue_io.bits := Reverse(concated_data)
+  io.out <> queue
+
+  when(cycle_counter.value === 0.U) {
+    concated_data := 0.U
+    received := false.B
+  }
+
+  when(ps2_clk_valid) {
+    when(cycle_counter.value < 9.U && cycle_counter.value >= 1.U) {
+      concated_data := (concated_data << 1) | io.ps2.data
+    }.elsewhen(cycle_counter.value === 9.U) {
+      received := true.B
+    }
+    cycle_counter.inc()
+  }
+
+  when(!pushed && received) {
+    queue_io.valid := true.B
+  }.elsewhen(pushed && received) {
+    queue_io.valid := false.B
+    received := false.B
+  }
+}
+
+class SegHandler(seg_count: Int) extends Module {
+  val io = IO(new Bundle {
+    val keycode = Flipped(Decoupled(UInt(8.W)))
+    val segs = Output(Vec(seg_count, UInt(4.W)))
+  })
+
+
+  val seg_regs = RegInit(VecInit(Seq.fill(seg_count)(0.U(4.W))))
+  val last_keycode = RegInit(0.U(8.W))
+  val counter = Counter(0xFF)
+  val digit_to_seg = Seq(
+    0.U -> "b0111111".U, // 0
+    1.U ->"b0000110".U, // 1
+    2.U -> "b1011011".U, // 2
+    3.U -> "b1001111".U, // 3
+    4.U -> "b1100110".U, // 4
+    5.U -> "b1101101".U, // 5
+    6.U -> "b1111101".U, // 6
+    7.U -> "b0000111".U, // 7
+    8.U -> "b1111111".U, // 8
+    9.U -> "b1101111".U, // 9
+    10.U -> "b1110111".U, // A
+    11.U -> "b1111100".U, // B
+    12.U -> "b0111001".U, // C
+    13.U -> "b1011110".U, // D
+    14.U -> "b1111001".U, // E
+    15.U -> "b1110001".U  // F
+  )
+  io.segs := seg_regs
+
+  when(io.keycode.valid) {
+    val data = io.keycode.bits
+    val state_f0_received = RegNext(data === 0xF0.U, false.B)
+    io.keycode.ready := true.B
+    // Handle keycode based on current state
+    // (keyboard press counter) :: (ASCII code) :: (Keycode)
+    when(state_f0_received) {
+      // Release code
+    }.otherwise{
+      counter.inc()
+      last_keycode := io.keycode.bits
+    }
+  }.otherwise {
+    io.keycode.ready := false.B
+  }
+  
+  seg_regs := Seq(counter.value, last_keycode, last_keycode).map(d => {
+    MuxLookup(d & 0xF.U, 0.U)(digit_to_seg) | (MuxLookup((d >> 4.U) & 0xF.U, 0.U)(digit_to_seg) << 4.U)
+  })
+}
+
+

npc/core/src/main/scala/Main.scala

@@ -1,7 +1,7 @@
 package npc
 
 import chisel3._
-import chisel3.util.{MuxLookup, Fill}
+import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
 import chisel3.stage.ChiselOption
 
 class RegisterFile(readPorts: Int) extends Module {
@@ -56,20 +56,6 @@ class ALUGenerator(width: Int) extends Module {
   ))
 }
 
-class MuxGenerator(width: Int, nInput: Int) extends Module {
-  require(width >= 0)
-  require(nInput >= 1)
-  require(nInput.toBinaryString.map(_ - '0').sum == 1)
-  
-  val io = IO(new Bundle {
-    val in = Input(Vec(nInput, UInt(width.W)))
-    val sel = Input(UInt(nInput.toBinaryString.reverse.indexOf('1').W))
-    val out = Output(UInt(width.W))
-  })
-
-  io.out := io.in(io.sel)
-}
-
 class Test extends Module {
   val io = IO(new Bundle {
     val in = Input(UInt(32.W))
@@ -93,3 +79,20 @@ class Switch extends Module {
 
   io.out := io.sw(0) ^ io.sw(1)
 }
+
+import npc.keyboard._
+
+class Keyboard extends Module {
+  val io = IO(new Bundle {
+    val ps2 = PS2Port()
+    val segs = Output(Vec(6, UInt(4.W)))
+  })
+
+  val keyboard_controller = new KeyboardController
+  val seg_handler = new SegHandler(6)
+
+  seg_handler.io.keycode <> keyboard_controller.io.out
+
+  io <> keyboard_controller.io
+  io <> seg_handler.io
+}

npc/core/src/main/scala/SegGenerator.scala

@@ -0,0 +1,35 @@
+package npc.seg
+
+import chisel3._
+import chisel3.util.{Decoupled}
+import chisel3.util.log2Ceil
+
+class SegInput(width: Int) extends Bundle {
+  require(width > 0)
+  val addr = UInt(width.W)
+  val value = UInt(log2Ceil(width).W)
+}
+
+object SegInput {
+  def apply(width: Int): SegInput = {
+    return new SegInput(width)
+  }
+}
+
+class SegGenerator(width: Int) extends {
+  val io = IO(new Bundle {
+    val write = Flipped(Decoupled(SegInput(8)))
+    val segs = Output(Vec(width, UInt(8.W)))
+  })
+
+  val seg_regs = RegInit(VecInit(Seq.fill(width)(0.U(8.W))))
+  io.segs := seg_regs
+
+  when(io.write.valid) {
+    val data = io.write.bits
+    seg_regs(data.addr) := data.value
+    io.write.ready := true.B
+  }.otherwise {
+    io.write.ready := false.B
+  }
+}