> configure(npc)
ysyx_22040000 李心杨 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux 20:30:51 up 1 day 19:31, 2 users, load average: 0.75, 0.84, 0.73
This commit is contained in:
tracer-ysyx
parent
d02c8f5681
commit
45b0983c4a
21 changed files with 290 additions and 780 deletions
110
npc/core/src/main/scala/Keyboard.scala
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110
npc/core/src/main/scala/Keyboard.scala
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@ -0,0 +1,110 @@
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package npc.keyboard
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import chisel3._
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import chisel3.util.{Counter, Decoupled, Queue, Reverse, MuxLookup}
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import npc.seg._
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class PS2Port extends Bundle {
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val clk = Input(Bool())
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val data = Input(UInt(1.W))
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}
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object PS2Port {
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def apply(): PS2Port = {
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new PS2Port
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}
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}
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class KeyboardController extends Module {
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val io = IO(new Bundle {
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val ps2 = PS2Port()
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val out = Decoupled(UInt(8.W))
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})
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// valid only on the clock negedge of ps2_clk
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val ps2_clk_valid = RegNext(io.ps2.clk, false.B) & ~io.ps2.clk
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val cycle_counter = Counter(11)
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val concated_data = RegInit(0.U(8.W))
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val queue_io = Wire(Flipped(Decoupled(UInt(8.W))))
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val queue = Queue(queue_io, entries = 8)
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val received = RegInit(Bool(), false.B)
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val pushed = RegNext(queue_io.valid && queue_io.ready, false.B)
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queue_io.valid := false.B
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queue_io.bits := Reverse(concated_data)
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io.out <> queue
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when(cycle_counter.value === 0.U) {
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concated_data := 0.U
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received := false.B
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}
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when(ps2_clk_valid) {
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when(cycle_counter.value < 9.U && cycle_counter.value >= 1.U) {
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concated_data := (concated_data << 1) | io.ps2.data
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}.elsewhen(cycle_counter.value === 9.U) {
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received := true.B
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}
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cycle_counter.inc()
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}
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when(!pushed && received) {
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queue_io.valid := true.B
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}.elsewhen(pushed && received) {
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queue_io.valid := false.B
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received := false.B
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}
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}
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class SegHandler(seg_count: Int) extends Module {
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val io = IO(new Bundle {
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val keycode = Flipped(Decoupled(UInt(8.W)))
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val segs = Output(Vec(seg_count, UInt(4.W)))
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})
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val seg_regs = RegInit(VecInit(Seq.fill(seg_count)(0.U(4.W))))
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val last_keycode = RegInit(0.U(8.W))
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val counter = Counter(0xFF)
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val digit_to_seg = Seq(
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0.U -> "b0111111".U, // 0
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1.U ->"b0000110".U, // 1
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2.U -> "b1011011".U, // 2
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3.U -> "b1001111".U, // 3
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4.U -> "b1100110".U, // 4
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5.U -> "b1101101".U, // 5
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6.U -> "b1111101".U, // 6
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7.U -> "b0000111".U, // 7
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8.U -> "b1111111".U, // 8
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9.U -> "b1101111".U, // 9
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10.U -> "b1110111".U, // A
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11.U -> "b1111100".U, // B
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12.U -> "b0111001".U, // C
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13.U -> "b1011110".U, // D
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14.U -> "b1111001".U, // E
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15.U -> "b1110001".U // F
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)
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io.segs := seg_regs
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when(io.keycode.valid) {
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val data = io.keycode.bits
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val state_f0_received = RegNext(data === 0xF0.U, false.B)
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io.keycode.ready := true.B
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// Handle keycode based on current state
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// (keyboard press counter) :: (ASCII code) :: (Keycode)
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when(state_f0_received) {
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// Release code
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}.otherwise{
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counter.inc()
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last_keycode := io.keycode.bits
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}
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}.otherwise {
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io.keycode.ready := false.B
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}
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seg_regs := Seq(counter.value, last_keycode, last_keycode).map(d => {
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MuxLookup(d & 0xF.U, 0.U)(digit_to_seg) | (MuxLookup((d >> 4.U) & 0xF.U, 0.U)(digit_to_seg) << 4.U)
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})
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}
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@ -1,7 +1,7 @@
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package npc
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import chisel3._
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import chisel3.util.{MuxLookup, Fill}
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import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
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import chisel3.stage.ChiselOption
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class RegisterFile(readPorts: Int) extends Module {
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@ -56,20 +56,6 @@ class ALUGenerator(width: Int) extends Module {
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))
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}
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class MuxGenerator(width: Int, nInput: Int) extends Module {
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require(width >= 0)
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require(nInput >= 1)
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require(nInput.toBinaryString.map(_ - '0').sum == 1)
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val io = IO(new Bundle {
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val in = Input(Vec(nInput, UInt(width.W)))
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val sel = Input(UInt(nInput.toBinaryString.reverse.indexOf('1').W))
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val out = Output(UInt(width.W))
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})
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io.out := io.in(io.sel)
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}
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class Test extends Module {
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val io = IO(new Bundle {
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val in = Input(UInt(32.W))
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@ -93,3 +79,20 @@ class Switch extends Module {
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io.out := io.sw(0) ^ io.sw(1)
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}
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import npc.keyboard._
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class Keyboard extends Module {
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val io = IO(new Bundle {
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val ps2 = PS2Port()
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val segs = Output(Vec(6, UInt(4.W)))
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})
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val keyboard_controller = new KeyboardController
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val seg_handler = new SegHandler(6)
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seg_handler.io.keycode <> keyboard_controller.io.out
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io <> keyboard_controller.io
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io <> seg_handler.io
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}
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35
npc/core/src/main/scala/SegGenerator.scala
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35
npc/core/src/main/scala/SegGenerator.scala
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@ -0,0 +1,35 @@
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package npc.seg
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import chisel3._
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import chisel3.util.{Decoupled}
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import chisel3.util.log2Ceil
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class SegInput(width: Int) extends Bundle {
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require(width > 0)
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val addr = UInt(width.W)
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val value = UInt(log2Ceil(width).W)
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}
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object SegInput {
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def apply(width: Int): SegInput = {
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return new SegInput(width)
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}
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}
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class SegGenerator(width: Int) extends {
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val io = IO(new Bundle {
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val write = Flipped(Decoupled(SegInput(8)))
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val segs = Output(Vec(width, UInt(8.W)))
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})
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val seg_regs = RegInit(VecInit(Seq.fill(width)(0.U(8.W))))
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io.segs := seg_regs
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when(io.write.valid) {
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val data = io.write.bits
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seg_regs(data.addr) := data.value
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io.write.ready := true.B
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}.otherwise {
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io.write.ready := false.B
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}
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}
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64
npc/core/src/test/scala/Keyboard.scala
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64
npc/core/src/test/scala/Keyboard.scala
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@ -0,0 +1,64 @@
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package npc.keyboard
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import chisel3._
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import chiseltest._
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import org.scalatest.freespec.AnyFreeSpec
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import chiseltest.simulator.WriteVcdAnnotation
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class KeyboardControllerSpec extends AnyFreeSpec with ChiselScalatestTester {
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def transfer(keycode: Int, clock: Clock, ps2: PS2Port) : Unit = {
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require(keycode >= 0 && keycode < 0xFF)
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var cycle = 0
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var keycode_remain = keycode << 1 // Shift 1 to do nothing at cycle 0
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var keycode_collect = 0
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ps2.data.poke(1)
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ps2.clk.poke(true)
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clock.step(1)
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for (cycle <- 0 until 9) {
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val last_digit = keycode_remain & 1
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ps2.clk.poke(true)
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ps2.data.poke(last_digit)
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clock.step(32)
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keycode_collect = keycode_collect | (last_digit << cycle)
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keycode_remain = keycode_remain >> 1
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ps2.clk.poke(false)
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clock.step(32)
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}
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for (_ <- 9 until 11) {
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ps2.clk.poke(true)
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clock.step(32)
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ps2.clk.poke(false)
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clock.step(32)
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}
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assert(keycode_collect >> 1 == keycode)
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clock.step(32)
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}
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"Simple test" in {
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test(new KeyboardController).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
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val data = Array(0xE4, 0xD4, 0xC4, 0xA9)
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data.foreach(d => {
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transfer(d, c.clock, c.io.ps2)
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c.io.out.valid.expect(1.U)
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c.io.out.bits.expect(d)
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c.io.out.ready.poke(1)
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c.clock.step(1)
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c.io.out.ready.poke(0)
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})
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data.foreach(d => {
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transfer(d, c.clock, c.io.ps2)
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})
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data.foreach(d => {
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c.io.out.valid.expect(1.U)
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c.io.out.bits.expect(d)
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c.io.out.ready.poke(1)
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c.clock.step(1)
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c.io.out.ready.poke(0)
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})
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}
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}
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"Keyboard Simulation" in {
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test(new Keyboard) { c =>
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}
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}
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}
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@ -3,6 +3,7 @@ package npc
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import chisel3._
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import chiseltest._
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import org.scalatest.freespec.AnyFreeSpec
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import chiseltest.simulator.WriteVcdAnnotation
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class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
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"RegisterFile should work" - {
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@ -41,97 +42,62 @@ class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
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class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
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"With 32 width, " - {
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val neg = (x: BigInt) => BigInt("FFFFFFFF", 16) - x + 1
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val not = (x: BigInt) => x ^ BigInt("FFFFFFFF", 16)
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val mask = BigInt("FFFFFFFF", 16)
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val oprands: List[(BigInt, BigInt)] = List(
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(5, 3), (101010, 101010), (0xFFFFFFFCL, 0xFFFFFFFFL), (4264115, 2)
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)
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val operations: Map[Int, (BigInt, BigInt) => BigInt] = Map(
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0 -> ((a: BigInt, b: BigInt) => (a + b) & mask),
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1 -> ((a: BigInt, b: BigInt) => (a + neg(b)) & mask),
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2 -> ((a, _) => not(a)),
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3 -> (_ & _),
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4 -> (_ | _),
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5 -> (_ ^ _),
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6 -> ((a, b) => if (a < b) 1 else 0),
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7 -> ((a, b) => if (a == b) 1 else 0),
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)
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val validate = (c: ALUGenerator,op: Int, oprands: List[(BigInt, BigInt)]) => {
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c.io.op.poke(op.U)
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oprands.foreach({ case (a, b) =>
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c.io.a.poke(a.U)
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c.io.b.poke(b.U)
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c.io.out.expect(operations(op)(a, b))
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})
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}
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"add should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(0.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(8.U)
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}
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test(new ALUGenerator(32)) { c => validate(c, 0, oprands) }
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}
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"sub should work" - {
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"with positive result" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(1.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(2)
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validate(c, 1, oprands.filter({case (a, b) => a >= b}))
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}
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}
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"with negative result" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(1.U)
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c.io.a.poke(3.U)
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c.io.b.poke(5.U)
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c.io.out.expect(BigInt("FFFFFFFF", 16) - 1)
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validate(c, 1, oprands.filter({case (a, b) => a < b}))
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}
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}
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}
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"not should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(2.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(BigInt("FFFFFFFA", 16))
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}
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test(new ALUGenerator(32)) { c => validate(c, 2, oprands) }
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}
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"and should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(3.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(1.U)
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}
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test(new ALUGenerator(32)) { c => validate(c, 3, oprands) }
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}
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"or should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(4.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(7.U)
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}
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test(new ALUGenerator(32)) { c => validate(c, 4, oprands) }
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}
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"xor should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(5.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(6.U)
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}
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test(new ALUGenerator(32)) { c => validate(c, 5, oprands) }
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}
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"compare should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(6)
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c.io.a.poke(62.U)
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c.io.b.poke(3.U)
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c.io.out.expect(0.U)
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c.io.a.poke(2.U)
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c.io.b.poke(103.U)
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c.io.out.expect(1.U)
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c.io.a.poke(16.U)
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c.io.b.poke(16.U)
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c.io.out.expect(0.U)
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}
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test(new ALUGenerator(32)) { c => validate(c, 6, oprands) }
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}
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"equal should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(7)
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c.io.a.poke(62.U)
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c.io.b.poke(3.U)
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c.io.out.expect(0.U)
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c.io.a.poke(2.U)
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c.io.b.poke(103.U)
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c.io.out.expect(0.U)
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c.io.a.poke(16.U)
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c.io.b.poke(16.U)
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c.io.out.expect(1.U)
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}
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test(new ALUGenerator(32)) { c => validate(c, 7, oprands) }
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}
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}
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}
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