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> sim RTL

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ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 19:50:34  up  22:48,  2 users,  load average: 0.25, 0.38, 0.46
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tracer-ysyx 2023-12-23 19:50:34 +08:00 • committed by xinyangli
parent a58f8d9020
commit 3b0310ef47
2 changed files with 34 additions and 2 deletions
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4
npc/Makefile
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@ -10,12 +10,12 @@ sim: all
$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
@echo "Running" $(OBJDIR)/Vexample "..."
@echo "================================"
$(OBJDIR)/Vexample
@$(OBJDIR)/Vexample
$(OBJDIR): $(VSRC) $(CPPSRC)
mkdir -p $(OBJDIR)
verilator --cc --exe --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
verilator --trace --cc --exe --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
include ../Makefile