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> sim RTL

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ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 17:27:29  up  20:25,  2 users,  load average: 0.48, 0.77, 0.76
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tracer-ysyx 2023-12-23 17:27:29 +08:00 • committed by xinyangli
parent 397cf4da54
commit 355bd72c8d
19 changed files with 709 additions and 12 deletions
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16
npc/Makefile Normal file
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@ -0,0 +1,16 @@
VERILATOR := verilator
VSRC := $(wildcard vsrc/*.v)
CPPSRC := $(wildcard csrc/*.cpp)
all:
@echo "Write this Makefile by your self."
sim: obj_dir
$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
@echo "Write this Makefile by your self."
obj_dir: $(VSRC) $(CPPSRC)
$(VERILATOR) $(VSRC:%=--cc %) $< $(CPPSRC:%=--exe %) --Mdir $@
include ../Makefile