npc,fix: bugs of new arch in cpu-tests

npc/core/build.sbt

@@ -1,7 +1,7 @@
 ThisBuild / scalaVersion := "2.13.12"
-ThisBuild / version := "0.1.0"
+ThisBuild / version := "0.1.1"
 
-val chiselVersion = "6.2.0"
+val chiselVersion = "6.5.0"
 val circeVersion = "0.14.1"
 
 lazy val root = (project in file("."))

npc/core/project/build.properties

@@ -1 +1 @@
-sbt.version=1.9.9
+sbt.version=1.10.1

npc/core/src/main/resources/RamDpi.v

@@ -1,4 +1,4 @@
-import "DPI-C" function int pmem_read(input int addr);
+import "DPI-C" function int pmem_read(input int addr, input byte rmask);
 import "DPI-C" function void pmem_write(input int waddr, input int wdata, input byte wmask);
 
 module RamDpi (
@@ -9,6 +9,7 @@ module RamDpi (
   input [31:0] writeAddr,
   input [31:0] writeData,
   input [3:0] writeMask,
+  input [3:0] readMask,
   input reg [31:0] readAddr,
   output reg [31:0] readData,
   input reg [31:0] pc,
@@ -16,7 +17,7 @@ module RamDpi (
 );
   always @(posedge clock) begin
     if (valid) begin // 有读写请求时
-      readData = pmem_read(readAddr);
+      readData = pmem_read(readAddr, { 4'h0, readMask });
       if (writeEnable) begin // 有写请求时
         pmem_write(writeAddr, writeData, { 4'h0, writeMask });
       end
@@ -25,5 +26,5 @@ module RamDpi (
       readData = 32'h80000000;
     end
   end
-  assign inst = pmem_read(pc);
+  assign inst = pmem_read(pc, 8'hF);
 endmodule

npc/core/src/main/scala/components/ALU.scala

@@ -94,7 +94,7 @@ class newALU(implicit p: Params) extends Module {
     val b = Input(Vec(SrcBSelect.all.length, UInt(p.XLEN)))
   })
   val out = IO(new Bundle {
-    val eq = Output(Bool())
+    val isEqual = Output(Bool())
     val result = Output(UInt(p.XLEN))
   })
 
@@ -113,7 +113,7 @@ class newALU(implicit p: Params) extends Module {
   val sll = a << b(5, 0)
   val srl = a >> b(5, 0)
   val sra = a.asSInt >> b(5, 0)
-  out.eq := a === b
+  out.isEqual := a === b
 
   import OpSelect._
 

npc/core/src/main/scala/components/Mem.scala

@@ -16,38 +16,14 @@ import chisel3.util.experimental.decode.{decoder, TruthTable}
 import flow.components.util._
 import flow.components.RV32Inst._
 
-class RamControlInterface(addrWidth: Int) extends Bundle {
-  val valid = Input(Bool())
-  val writeMask = Input(UInt((addrWidth / 8).W))
-  val writeEnable = Input(Bool())
-  def ctrlBindPorts = {
-    valid :: writeMask :: writeEnable :: HNil
-  }
-
-}
-
-/* FIXME: Extends here might not be the best solution.
- *        We need a way to merge two bundles together
- */
-class RamInterface[T <: Data](tpe: T, addrWidth: Int)
-    extends RamControlInterface(addrWidth) {
-  val clock = Input(Clock())
-  val reset = Input(Reset())
-  val writeAddr = Input(UInt(addrWidth.W))
-  val writeData = Input(tpe)
-  val readAddr = Input(UInt(addrWidth.W))
-  val readData = Output(tpe)
-  val pc = Input(UInt(addrWidth.W))
-  val inst = Output(tpe)
-}
-
-class RamDpi extends BlackBox with HasBlackBoxResource {
-  val io = IO((new RamInterface(UInt(32.W), 32)))
+class RamDpi(implicit p: Params) extends BlackBox with HasBlackBoxResource {
+  val io = IO(new DpiRamInterface)
   addResource("/RamDpi.v")
 }
 
 class DpiRamControlInterface(implicit p: Params) extends Bundle {
   val valid = Input(Bool())
+  val readMask = Input(UInt((p.XLEN.get / 8).W))
   val writeMask = Input(UInt((p.XLEN.get / 8).W))
   val writeEnable = Input(Bool())
 }
@@ -84,6 +60,15 @@ class RamController(implicit p: Params) extends Module {
     BitPat.dontCare(out.writeMask.getWidth)
   )
 
+  private val readMaskMapping = TruthTable(
+    Array(
+      lb -> BitPat("b0001"),
+      lh -> BitPat("b0011"),
+      lw -> BitPat("b1111")
+    ),
+    BitPat.dontCare(out.readMask.getWidth)
+  )
+
   private val writeEnableMapping = TruthTable(
     Array(
       sb -> BitPat("b1"),
@@ -94,6 +79,7 @@ class RamController(implicit p: Params) extends Module {
   )
 
   out.valid := decoder(in.inst, validMapping)
-  out.writeEnable := decoder(in.inst, writeMaskMapping)
+  out.writeEnable := decoder(in.inst, writeEnableMapping)
   out.writeMask := decoder(in.inst, writeMaskMapping)
+  out.readMask := decoder(in.inst, readMaskMapping)
 }

npc/core/src/main/scala/components/ProgramCounter.scala

@@ -72,7 +72,7 @@ class newProgramCounter(implicit p: Params) extends Module {
   val control = IO(newPcControlInterface())
   import newPcControlInterface.SrcSelect._
   val in = IO(new Bundle {
-    val brAddr = Input(UInt(p.XLEN))
+    val brOffset = Input(UInt(p.XLEN))
     val jAddr = Input(UInt(p.XLEN))
   })
   val out = IO(Output(UInt(p.XLEN)))
@@ -83,8 +83,8 @@ class newProgramCounter(implicit p: Params) extends Module {
   private val npc = MuxLookup(control.srcSelect, 4.U)(
     Seq(
       pStatic -> (pcReg + 4.U),
-      pJmp -> in.brAddr,
-      pBR -> in.jAddr
+      pJmp -> in.jAddr,
+      pBR -> (pcReg + in.brOffset)
     )
   )
 

npc/core/src/main/scala/components/RegisterFile.scala

@@ -58,8 +58,6 @@ class RegisterFile[T <: Data](tpe: T, regCount: Int, numReadPorts: Int)
   for (port <- 0 until numReadPorts) {
     out.src(port) := regFile(in.rs(port).asUInt)
   }
-  traceName(regFile)
-  dontTouch(regFile)
 }
 
 class newRegisterFile(implicit p: Params) extends Module {
@@ -94,6 +92,8 @@ class newRegisterFile(implicit p: Params) extends Module {
 
   out.src1 := regFile(in.rs1)
   out.src2 := regFile(in.rs2)
+  traceName(regFile)
+  dontTouch(regFile)
 }
 
 class RegisterFileController(implicit p: Params) extends Module {
@@ -124,18 +124,20 @@ class RegisterFileController(implicit p: Params) extends Module {
   // format: on
 
   private val writeSelectMapping = TruthTable(
-    memOutMapping ++ npcMapping,
+    aluOutMapping ++ memOutMapping ++ npcMapping,
     BitPat.dontCare(out.writeSelect.getWidth)
   )
 
   // enable write if instruction belongs to any mapping above
   private val writeEnableMapping = TruthTable(
     (aluOutMapping ++ memOutMapping ++ npcMapping).map(x =>
-      (x._1 -> BitPat(true.B))
+      (x._1 -> BitPat("b1"))
     ),
-    BitPat(false.B)
+    BitPat("b0")
   )
 
+  println(writeEnableMapping)
+
   out.writeSelect := RegControl.WriteSelect
     .safe(
       decoder(in.inst, writeSelectMapping)

npc/core/src/main/scala/stages/EX.scala

@@ -34,31 +34,34 @@ class EX(implicit val p: Params) extends Module {
   {
     import flow.components.ALUControlInterface.SrcASelect._
     import flow.components.util.chiselEnumAsInt
-    alu.in.a(aSrcARs1) := _in.inst.rs1
+    alu.in.a(aSrcARs1) := _in.src1
     alu.in.a(aSrcAPc) := _in.pc
     alu.in.a(aSrcAZero) := 0.U
 
     import flow.components.ALUControlInterface.SrcBSelect._
-    alu.in.b(aSrcBRs2) := _in.inst.rs2
+    alu.in.b(aSrcBRs2) := _in.src2
     alu.in.b(aSrcBImmI) := _in.inst.immI
     alu.in.b(aSrcBImmJ) := _in.inst.immJ
     alu.in.b(aSrcBImmU) := _in.inst.immU
     alu.in.b(aSrcBImmS) := _in.inst.immS
   }
 
-  _out.exeEq := alu.out.result
-  _out.exeOut := alu.out.eq
+  _out.exeOut := alu.out.result
 
   _toIF.jAddr := alu.out.result
-  _toIF.brAddr := _in.inst.immB
+  _toIF.brOffset := _in.inst.immB
+  _toIF.pc := _in.pc
 
   import flow.components.newPcControlInterface.SrcSelect._
+  val regSrcEq = Wire(Bool());
+  regSrcEq := (_in.src1 === _in.src2);
   when(_in.pcCtrl.srcSelect === pBR) {
     val branchUseSlt = _in.inst(14)
     val branchInvertResult = _in.inst(12)
-    val _branchResult = Mux(branchUseSlt, alu.out.result(0), alu.out.eq)
+    val _branchResult =
+      Mux(branchUseSlt, alu.out.result(0), regSrcEq)
     val branchResult = Mux(branchInvertResult, !_branchResult, _branchResult)
-    _toIF.pcCtrl.srcSelect := Mux(branchInvertResult, pBR, pStatic)
+    _toIF.pcCtrl.srcSelect := Mux(branchResult, pBR, pStatic)
   }.otherwise {
     _toIF.pcCtrl.srcSelect := _in.pcCtrl.srcSelect
   }

npc/core/src/main/scala/stages/ID.scala

@@ -7,6 +7,8 @@ import flow.stages.messages._
 import flow.components._
 import flow.components.RV32InstSubfields._
 import chisel3.util.DecoupledIO
+import chisel3.experimental.Trace._
+import chisel3.util.experimental.InlineInstance
 
 class ID(implicit val p: Params) extends Module {
   val io = IO(new Bundle {
@@ -25,7 +27,7 @@ class ID(implicit val p: Params) extends Module {
   val _out = msgio.out.bits
   val _fromWB = io.fromWB
 
-  val regs = Module(new newRegisterFile)
+  val regs = Module(new newRegisterFile with InlineInstance)
 
   // Controllers
   val pcController = Module(new PcController)

npc/core/src/main/scala/stages/IF.scala

@@ -34,7 +34,7 @@ class IF(implicit val p: Params) extends Module {
   private val pc = Module(new newProgramCounter)
 
   // PC update
-  pc.in.brAddr := _fromEx.brAddr
+  pc.in.brOffset := _fromEx.brOffset
   pc.in.jAddr := _fromEx.jAddr
 
   pc.control := _fromEx.pcCtrl

npc/core/src/main/scala/stages/LS.scala

@@ -30,8 +30,10 @@ class LS(implicit val p: Params) extends Module {
   ram.io.clock := clock
   ram.io.reset := reset
   ram.io.writeAddr := _in.exeOut
-  ram.io.writeData := _in.src1
+  ram.io.writeData := _in.src2
   ram.io.writeMask := _in.ramCtrl.writeMask
+  ram.io.readMask := _in.ramCtrl.readMask
+
   ram.io.writeEnable := _in.ramCtrl.writeEnable
   ram.io.valid := _in.ramCtrl.valid // TODO: change to a better name
   ram.io.readAddr := _in.exeOut
@@ -39,7 +41,7 @@ class LS(implicit val p: Params) extends Module {
   // TODO: Change to icache, and move to IF stage.
   // Change to arbitor here
   ram.io.pc := _fromIF.pc
-  _toIF.inst := ram.io.pc
+  _toIF.inst := ram.io.inst
 
   _out.memOut := ram.io.readData
   _out.exeOut := _in.exeOut

npc/core/src/main/scala/stages/Messages.scala

@@ -30,7 +30,6 @@ class EX2LS(implicit p: Params) extends Bundle {
   val src2 = UInt(p.XLEN)
 
   val exeOut = UInt(p.XLEN)
-  val exeEq = Bool()
 
   // Control
   val ramCtrl = Flipped(new DpiRamControlInterface)
@@ -47,7 +46,8 @@ class LS2WB(implicit p: Params) extends Bundle {
 }
 
 class EX2IF(implicit p: Params) extends Bundle {
-  val brAddr = UInt(p.XLEN)
+  val pc = UInt(p.XLEN)
+  val brOffset = UInt(p.XLEN)
   val jAddr = UInt(p.XLEN)
 
   // Control

npc/core/src/main/scala/stages/WB.scala

@@ -6,6 +6,7 @@ import chisel3.util.DecoupledIO
 import flow.Params
 import flow.stages.utils._
 import flow.stages.messages._
+import chisel3.experimental.Trace._
 
 class WB(implicit val p: Params) extends Module {
   // val msgio = IO(DecoupledMsgIO(in = (new LS2WB).S))
@@ -25,4 +26,7 @@ class WB(implicit val p: Params) extends Module {
   _toID.regCtrl := _in.regCtrl;
   _toID.rd := _in.rd
   _toID.npc := _in.pc + 4.U
+
+  traceName(_in.pc)
+  traceName(_in.rd)
 }

npc/core/src/main/scala/top/FlowMain.scala

@@ -13,7 +13,7 @@ import chisel3.util.{BinaryMemoryFile, HexMemoryFile}
 import chisel3.experimental.Trace
 import scala.collection.IndexedSeqView
 import shapeless.Poly1
-import flow.components.RamControlInterface
+import flow.components.DpiRamControlInterface
 import flow.components.RV32Inst
 import flow.components.RV32InstSubfields._
 import flow.components.util._
@@ -21,6 +21,11 @@ import flow.components.util._
 import flow.components.{RegControl, PcControlInterface, ALUControlInterface}
 
 import flow.stages._
+import chisel3.experimental.annotate
+import chisel3.experimental.ChiselAnnotation
+
+import chisel3.Data
+import chisel3.experimental.{annotate, requireIsAnnotatable, ChiselAnnotation}
 
 class Flow extends Module {
   implicit val p: Params = new Params(XLEN = 32.W, arch = "single")
@@ -40,448 +45,3 @@ class Flow extends Module {
   LS.io.fromIF := IF.io.toRam
   ID.io.fromWB := WB.io.toID
 }
-
-// class Control(width: Int) extends RawModule {
-//   // Helpers
-//   class WrapList[T](vl: T) { type Type = T; val v = vl }
-//   object wrap extends Poly1 {
-//     implicit def default[A] = at[A](Right(_).withLeft[Int])
-//   }
-//   def lit(x: Element) = { x.litValue.toInt }
-//   def toBits(t: dst.Type): BitPat = {
-//     val list = t.toList
-//     list
-//       .map(e =>
-//         e match {
-//           case Right(x) => BitPat(lit(x).U(x.getWidth.W))
-//           case Left(x)  => BitPat.dontCare(x)
-//         }
-//       )
-//       .reduceLeft(_ ## _)
-//   }
-//   val r = Right
-//   def l[T <: Any](x: T) = x match {
-//     case x: ChiselEnum => Left(log2Ceil(x.all.length))
-//     case x: Data       => Left(x.getWidth)
-//     case _             => throw new IllegalArgumentException
-//   }
-//
-//   val inst = IO(Input(UInt(width.W)))
-//
-//   val reg = IO(Flipped(RegControl()))
-//   val pc = IO(Flipped(PcControlInterface()))
-//   val alu = IO(Flipped(ALUControlInterface()))
-//   val ram = IO(Flipped(RamControlInterface(32)))
-//
-//   val dst = new WrapList(
-//     (reg.ctrlBindPorts ++
-//       pc.ctrlBindPorts ++
-//       alu.ctrlBindPorts ++
-//       ram.ctrlBindPorts).map(wrap)
-//   )
-//
-//   val dstList = dst.v.toList
-//   val controlWidth = dstList.map(_.toOption.get.getWidth).reduce(_ + _)
-//   val reversePrefixSum = dstList.scanLeft(0)(_ + _.toOption.get.getWidth)
-//   val sliceIndex = reversePrefixSum.map(controlWidth - _)
-//   val slices = sliceIndex.map(_ - 1).zip(sliceIndex.tail)
-//
-//   import reg.WriteSelect._
-//   import reg._
-//   import pc.SrcSelect._
-//   import pc._
-//   import alu.OpSelect._
-//   import alu.SrcASelect._
-//   import alu.SrcBSelect._
-//   import pc._
-//   import RV32Inst._
-//   // format: off
-//   val ControlMapping: Array[(BitPat, dst.Type)] = Array(
-//     //     Regs | writeEnable :: writeSelect :: HNil
-//     //     PC   | useImmB :: srcSelect :: HNil
-//     //     Exe  | op :: srcASelect :: srcBSelect :: signExt :: HNil
-//     //     Mem  | valid :: writeMask :: writeEnable :: HNil
-//
-//     (lui   , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc)::
-//       r(aOpAdd)     :: r(aSrcAZero)  :: r(aSrcBImmU) :: r(false.B) ::
-//       r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (auipc , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc)::
-//       r(aOpAdd)     :: r(aSrcAPc)  :: r(aSrcBImmU) :: r(false.B) ::
-//       r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     // ---- Control Transfer Instructions ----
-//     (jal   , (
-//       r(true.B)     :: r(rNpc)     ::
-//       r(false.B)    :: r(pExeOut)  ::
-//       r(aOpAdd)     :: r(aSrcAPc)  :: r(aSrcBImmJ) :: r(false.B) ::
-//       r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (jalr  , (
-//       r(true.B)     :: r(rNpc)     ::
-//       r(false.B)    :: r(pExeOut)    ::
-//       r(aOpAdd)     :: r(aSrcARs1) :: r(aSrcBImmI) :: r(false.B) ::
-//       r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (beq   , (
-//       r(false.B)    :: l(WriteSelect) ::
-//       r(true.B)     :: r(pStaticNpc)     ::
-//       r(aOpSlt)     :: r(aSrcARs1)  :: r(aSrcBRs2) :: l(Bool())    ::
-//       r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (bne   , (
-//       r(false.B)    :: l(WriteSelect) ::
-//       r(true.B)     :: r(pStaticNpc)     ::
-//       r(aOpSlt)     :: r(aSrcARs1)  :: r(aSrcBRs2) :: l(Bool())    ::
-//       r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (blt   , (
-//       r(false.B)    :: l(WriteSelect) ::
-//       r(true.B)     :: r(pStaticNpc)     ::
-//       r(aOpSlt)     :: r(aSrcARs1)  :: r(aSrcBRs2) :: r(true.B)  ::
-//       r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (bge   , (
-//       r(false.B)    :: l(WriteSelect) ::
-//       r(true.B)     :: r(pStaticNpc)     ::
-//       r(aOpSlt)     :: r(aSrcARs1)  :: r(aSrcBRs2) :: r(true.B)  ::
-//       r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (bltu  , (
-//       r(false.B)    :: l(WriteSelect)::
-//       r(true.B)     :: r(pStaticNpc)    ::
-//       r(aOpSltu)     :: r(aSrcARs1)    :: r(aSrcBRs2) :: r(false.B) ::
-//       r(false.B)    :: l(UInt(4.W))  :: r(false.B)   :: HNil
-//     )),
-//
-//     (bgeu  , (
-//       r(false.B)    :: l(WriteSelect)::
-//       r(true.B)     :: r(pStaticNpc)    ::
-//       r(aOpSltu)     :: r(aSrcARs1)    :: r(aSrcBRs2) :: r(false.B) ::
-//       r(false.B)    :: l(UInt(4.W))  :: r(false.B)   :: HNil
-//     )),
-//
-//     // ---- Memory Access Instructions ----
-//
-//     (lb    , (
-//       r(true.B)     :: r(rMemOut)    ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpAdd)     :: r(aSrcARs1)   :: r(aSrcBImmI) :: l(Bool()) ::
-//       r(true.B)     :: r(1.U(4.W))  :: r(false.B)   :: HNil
-//     )),
-//
-//     (lbu   , (
-//       r(true.B)    :: r(rMemOut)    ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpAdd)     :: r(aSrcARs1)   :: r(aSrcBImmI) :: l(Bool()) ::
-//       r(true.B)     :: r(0.U(4.W))  :: r(false.B)   :: HNil
-//     )),
-//
-//     (lh     , (
-//       r(true.B)    :: r(rMemOut)    ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpAdd)     :: r(aSrcARs1)   :: r(aSrcBImmI) :: l(Bool()) ::
-//       r(true.B)     :: r(3.U(4.W))  :: r(false.B)   :: HNil
-//     )),
-//
-//     (lhu    , (
-//       r(true.B)    :: r(rMemOut)    ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpAdd)     :: r(aSrcARs1)   :: r(aSrcBImmI) :: l(Bool()) ::
-//       r(true.B)     :: r(2.U(4.W))  :: r(false.B)   :: HNil
-//     )),
-//
-//     (lw    , (
-//       r(true.B)     :: r(rMemOut)    ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpAdd)     :: r(aSrcARs1)   :: r(aSrcBImmI) :: l(Bool()) ::
-//       r(true.B)     :: r(14.U(4.W))  :: r(false.B)   :: HNil
-//     )),
-//
-//     (sb    , (
-//       r(false.B)    :: l(WriteSelect)::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpAdd)     :: r(aSrcARs1)   :: r(aSrcBImmS) :: l(Bool()) ::
-//       r(true.B)     :: r(1.U(4.W))   :: r(true.B)   :: HNil
-//     )),
-//
-//     (sh    , (
-//       r(false.B)    :: l(WriteSelect)::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpAdd)     :: r(aSrcARs1)   :: r(aSrcBImmS) :: l(Bool()) ::
-//       r(true.B)     :: r(3.U(4.W))   :: r(true.B)   :: HNil
-//     )),
-//
-//     (sw    , (
-//       r(false.B)    :: l(WriteSelect)::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpAdd)     :: r(aSrcARs1)   :: r(aSrcBImmS) :: l(Bool()) ::
-//       r(true.B)     :: r(15.U(4.W))  :: r(true.B)   :: HNil
-//     )),
-//
-//     // ---- Integer Computational Instructions ---
-//
-//     (addi  , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpAdd)     :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool())    ::
-//       r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (slti  , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpSlt)     :: r(aSrcARs1) :: r(aSrcBImmI) :: r(true.B)  ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (sltiu , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpSltu)     :: r(aSrcARs1) :: r(aSrcBImmI) :: r(false.B) ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (xori  , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpXor)      :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool())    ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (ori   , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpOr)     :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool())    ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (andi  , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpAnd)     :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool())    ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (slli  , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpSll)     :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool())    ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (srli  , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpSrl)     :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool())    ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (srai  , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpSra)     :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool())    ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (add   , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpAdd)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: l(Bool())    ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (sub   , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpSub)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: l(Bool())    ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (sll   , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpSll)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: l(Bool())    ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (slt   , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpSlt)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: r(true.B)  ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (sltu  , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpSltu)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: r(false.B) ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (xor   , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpXor)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: l(Bool())    ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (srl   , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpSrl)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: l(Bool())    ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (sra   , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpSra)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: l(Bool())    ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (or    , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpOr)      :: r(aSrcARs1) :: r(aSrcBRs2)  :: l(Bool())    ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//
-//     (and   , (
-//       r(true.B)     :: r(rAluOut)  ::
-//       r(false.B)    :: r(pStaticNpc) ::
-//       r(aOpAnd)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: l(Bool())    ::
-//       r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
-//     )),
-//   )
-//   // format: on
-//
-//   val default = BitPat(0.U(controWidth.W))
-//
-// //   println(s"ControlMapping = ${ControlMapping.map(it => (it._1 -> toBits(it._2))).foreach(x => println(x._2))}\n")
-//   val out = decoder(
-//     inst,
-//     TruthTable(ControlMapping.map(it => (it._1 -> toBits(it._2))), default)
-//   )
-//   val srcList = slices.map(s => out(s._1, s._2))
-//
-//   assert(out != default)
-//   println(s"out = $out, default = $default\n")
-//   println(s"dstList = ${dstList}\n")
-//   println(s"srcList = ${srcList}\n")
-//   srcList
-//     .zip(dstList)
-//     .foreach({ case (src, dst) =>
-//       dst.toOption.get := src.asTypeOf(dst.toOption.get)
-//     })
-// }
-
-// class Flow extends Module {
-//   def lit(x: Data) = { x.litValue.toInt }
-//
-//   val dataType = UInt(32.W)
-//   val ram = Module(new RamDpi)
-//   val control = Module(new Control(32))
-//   val reg = Module(new RegisterFile(dataType, 32, 2))
-//   val pc = Module(new ProgramCounter(dataType))
-//   val alu = Module(new ALU(dataType))
-//
-//   // TODO: Switch to Decoupled and Arbiter later
-//   ram.io.pc := pc.out
-//   val inst = ram.io.inst
-//
-//   dontTouch(reg.control.writeEnable)
-//
-//   import control.pc.SrcSelect._
-//
-//   val npc = Wire(dataType)
-//   npc := pc.out + 4.U
-//   pc.in.exeOut := alu.out.result
-//   pc.in.immB := inst.immB
-//
-//   control.inst := inst
-//   reg.control <> control.reg
-//   // FIXME: Probably optimizable with bulk connection
-//   pc.control <> control.pc
-//   pc.control.useImmB := control.pc.useImmB
-//   alu.control <> control.alu
-//   val branchUseSlt = Wire(Bool())
-//   val branchInvertResult = Wire(Bool())
-//   branchUseSlt := inst(14)
-//   branchInvertResult := inst(12)
-//   val _branchResult = Mux(branchUseSlt, alu.out.result(0), alu.out.eq)
-//   val branchResult = Mux(branchInvertResult, !_branchResult, _branchResult)
-//   pc.control.useImmB := control.pc.useImmB && branchResult
-//   // printf(cf"_branchResult = ${_branchResult}, branchResult = ${branchResult}\n")
-//   // printf(cf"pcin.useImmB = ${pc.control.useImmB}, control.out.useImmB = ${control.pc.useImmB} \n")
-//
-//   import control.reg.WriteSelect._
-//   reg.in.writeData(rAluOut) := alu.out.result
-//   val maskedData = ram.io.readData & Cat(
-//     Fill(8, ram.io.writeMask(3)),
-//     Fill(8, ram.io.writeMask(2)),
-//     Fill(8, ram.io.writeMask(1)),
-//     "b11111111".U
-//   )
-//
-//   val doSignExt = control.ram.writeMask(0)
-//   val signExt16 = control.ram.writeMask(1)
-//   when(!doSignExt) {
-//     reg.in.writeData(rMemOut) := maskedData
-//     // printf(cf"!doSignExt\n")
-//   }.elsewhen(signExt16) {
-//     reg.in.writeData(rMemOut) := Cat(
-//       Fill(16, maskedData(15)),
-//       maskedData(15, 0)
-//     )
-//     // printf(cf"elsewhen\n")
-//   }.otherwise {
-//     reg.in
-//       .writeData(rMemOut) := Cat(Fill(24, maskedData(7)), maskedData(7, 0))
-//     // printf(cf"otherwise\n")
-//   }
-//   // printf(cf"maskedData = ${maskedData}, writeData = ${reg.in.writeData(lit(rMemOut))}\n")
-//   reg.in.writeData(rNpc) := npc
-//
-//   reg.in.writeAddr := inst.rd
-//   reg.in.rs(0) := inst.rs1
-//   reg.in.rs(1) := inst.rs2
-//
-//   // TODO: Bulk connection here
-//   ram.io.clock := clock
-//   ram.io.reset := reset
-//   ram.io.writeAddr := alu.out.result
-//   ram.io.writeData := reg.out.src(1)
-//   ram.io.writeMask := control.ram.writeMask
-//   ram.io.writeEnable := control.ram.writeEnable
-//   ram.io.valid := control.ram.valid
-//   ram.io.readAddr := alu.out.result
-//
-//   import control.alu.SrcASelect._
-//   import control.alu.SrcBSelect._
-//   alu.in.a(aSrcARs1) := reg.out.src(0)
-//   alu.in.a(aSrcAPc) := pc.out
-//   alu.in.a(aSrcAZero) := 0.U
-//
-//   alu.in.b(aSrcBRs2) := reg.out.src(1)
-//   // alu.in.b(lit(aSrcBImmI)) := inst(31, 20).pad(aSrcBImmI.getWidth)
-//   alu.in.b(aSrcBImmI) := inst.immI
-//   alu.in.b(aSrcBImmJ) := inst.immJ
-//   alu.in.b(aSrcBImmS) := inst.immS
-//   alu.in.b(aSrcBImmU) := inst.immU
-//
-//   Trace.traceName(pc.out)
-//   dontTouch(control.out)
-// }

npc/core/src/main/scala/top/Main.scala

@@ -7,10 +7,10 @@ import chisel3.experimental.Trace._
 import chisel3.stage.{ChiselGeneratorAnnotation, DesignAnnotation}
 import chisel3.util.experimental.InlineInstance
 import circt.stage.ChiselStage
-import firrtl.annotations.TargetToken.{Instance, OfModule, Ref}
 import java.io.PrintWriter
 import scala.io.Source
 import java.io.File
+import firrtl.annotations.TargetToken.{OfModule, Instance, Ref}
 
 // TODO: Generate verilator config file