> configure(npc)

ysyx_22040000 李心杨
 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux
  12:59:00  up 1 day 21:45,  2 users,  load average: 1.24, 1.19, 0.81
This commit is contained in:
tracer-ysyx 2024-01-06 12:59:00 +08:00 committed by xinyangli
parent 323e36c454
commit 239492c366
4 changed files with 155 additions and 173 deletions

View file

@ -25,6 +25,36 @@ class RegisterFile(readPorts: Int) extends Module {
}
}
class ALUGenerator(width: Int) extends Module {
require(width >= 0)
val io = IO(new Bundle {
val a = Input(UInt(width.W))
val b = Input(UInt(width.W))
val op = Input(UInt(4.W))
val out = Output(UInt(width.W))
})
val adder_b = fill(width)(io.op(0)) ^ io.b // take (-b) if sub
val add = io.a + adder_b
val and = io.a & io.b
val not = ~io.a
val or = io.a | io.b
val xor = io.a ^ io.b
val slt = io.a < io.b
val eq = io.a === io.b
io.out := MuxLookup(0.U, io.op, Seq(
0.U -> add,
1.U -> add, // add with b reversed
2.U -> not,
3.U -> and,
4.U -> or,
5.U -> xor,
6.U -> slt,
7.U -> eq,
))
}
class MuxGenerator(width: Int, nInput: Int) extends Module {
require(width >= 0)
require(nInput >= 1)

View file

@ -0,0 +1,125 @@
import chisel3._
import chiseltest._
import org.scalatest.freespec.AnyFreeSpec
class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
"RegisterFile should work" - {
"with 2 read ports" in {
test(new RegisterFile(2)) { c =>
def readExpect(addr: Int, value: Int, port: Int = 0): Unit = {
c.io.readAddr(port).poke(addr.U)
c.io.readData(port).expect(value.U)
}
def write(addr: Int, value: Int): Unit = {
c.io.writeEnable.poke(true.B)
c.io.writeData.poke(value.U)
c.io.writeAddr.poke(addr.U)
c.clock.step(1)
c.io.writeEnable.poke(false.B)
}
// everything should be 0 on init
for (i <- 0 until 32) {
readExpect(i, 0, port = 0)
readExpect(i, 0, port = 1)
}
// write 5 * addr + 3
for (i <- 0 until 32) {
write(i, 5 * i + 3)
}
// check that the writes worked
for (i <- 0 until 32) {
readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2)
}
}
}
}
}
class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
"With 32 width, " - {
"add should work" in {
test(new ALUGenerator(32)) { c =>
c.io.op.poke(0.U)
c.io.a.poke(5.U)
c.io.b.poke(3.U)
c.io.out.expect(8.U)
}
}
"sub should work" in {
test(new ALUGenerator(32)) { c =>
c.io.op.poke(1.U)
c.io.a.poke(5.U)
c.io.b.poke(3.U)
c.io.out.expect(2.U)
}
}
"not should work" in {
test(new ALUGenerator(32)) { c =>
c.io.op.poke(2.U)
c.io.a.poke(5.U)
c.io.b.poke(3.U)
c.io.out.expect((-6).U)
}
}
"and should work" in {
test(new ALUGenerator(32)) { c =>
c.io.op.poke(3.U)
c.io.a.poke(5.U)
c.io.b.poke(3.U)
c.io.out.expect(1.U)
}
}
"or should work" in {
test(new ALUGenerator(32)) { c =>
c.io.op.poke(4.U)
c.io.a.poke(5.U)
c.io.b.poke(3.U)
c.io.out.expect(7.U)
}
}
"xor should work" in {
test(new ALUGenerator(32)) { c =>
c.io.op.poke(5.U)
c.io.a.poke(5.U)
c.io.b.poke(3.U)
c.io.out.expect(6.U)
}
}
"compare should work" in {
test(new ALUGenerator(32)) { c =>
c.io.op.poke(6)
c.io.a.poke(62.U)
c.io.b.poke(3.U)
c.io.out.expect(0.U)
c.io.a.poke(2.U)
c.io.b.poke(103.U)
c.io.out.expect(1.U)
c.io.a.poke(16.U)
c.io.b.poke(16.U)
c.io.out.expect(1.U)
}
}
"equal should work" in {
test(new ALUGenerator(32)) { c =>
c.io.op.poke(7)
c.io.a.poke(62.U)
c.io.b.poke(3.U)
c.io.out.expect(0.U)
c.io.a.poke(2.U)
c.io.b.poke(103.U)
c.io.out.expect(0.U)
c.io.a.poke(16.U)
c.io.b.poke(16.U)
c.io.out.expect(1.U)
}
}
}
}

View file

@ -1,71 +0,0 @@
import chisel3._
import chiseltest._
import org.scalatest.freespec.AnyFreeSpec
class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
"RegisterFile should work" - {
"with 2 read ports" in {
test(new RegisterFile(2)) { c =>
def readExpect(addr: Int, value: Int, port: Int = 0): Unit = {
c.io.readAddr(port).poke(addr.U)
c.io.readData(port).expect(value.U)
}
def write(addr: Int, value: Int): Unit = {
c.io.writeEnable.poke(true.B)
c.io.writeData.poke(value.U)
c.io.writeAddr.poke(addr.U)
c.clock.step(1)
c.io.writeEnable.poke(false.B)
}
// everything should be 0 on init
for (i <- 0 until 32) {
readExpect(i, 0, port = 0)
readExpect(i, 0, port = 1)
}
// write 5 * addr + 3
for (i <- 0 until 32) {
write(i, 5 * i + 3)
}
// check that the writes worked
for (i <- 0 until 32) {
readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2)
}
}
}
}
}
class MuxGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
"MuxGenerator should work" - {
"when there are 2 inputs" in {
test(new MuxGenerator(8, 2)) { c =>
c.io.in(0).poke(0.U)
c.io.in(1).poke(1.U)
c.io.sel.poke(0.U)
c.io.out.expect(0.U)
c.io.sel.poke(1.U)
c.io.out.expect(1.U)
}
}
"when there are 1024 inputs" in {
test(new MuxGenerator(32, 1024)) { c =>
for (i <- 0 until 1024) {
c.io.in(i).poke(i.U)
}
for (i <- 0 until 1024) {
c.io.sel.poke(i.U)
c.io.out.expect(i.U)
}
}
}
}
"MuxGenerator should raise exception" - {
"when nInput is not 2^n" in {
assertThrows[IllegalArgumentException] {
test(new MuxGenerator(8, 3)) { c => }
}
}
}
}