> configure(npc)
ysyx_22040000 李心杨 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux 12:59:00 up 1 day 21:45, 2 users, load average: 1.24, 1.19, 0.81
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323e36c454
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239492c366
4 changed files with 155 additions and 173 deletions
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@ -25,6 +25,36 @@ class RegisterFile(readPorts: Int) extends Module {
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}
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}
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class ALUGenerator(width: Int) extends Module {
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require(width >= 0)
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val io = IO(new Bundle {
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val a = Input(UInt(width.W))
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val b = Input(UInt(width.W))
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val op = Input(UInt(4.W))
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val out = Output(UInt(width.W))
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})
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val adder_b = fill(width)(io.op(0)) ^ io.b // take (-b) if sub
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val add = io.a + adder_b
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val and = io.a & io.b
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val not = ~io.a
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val or = io.a | io.b
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val xor = io.a ^ io.b
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val slt = io.a < io.b
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val eq = io.a === io.b
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io.out := MuxLookup(0.U, io.op, Seq(
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0.U -> add,
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1.U -> add, // add with b reversed
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2.U -> not,
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3.U -> and,
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4.U -> or,
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5.U -> xor,
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6.U -> slt,
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7.U -> eq,
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))
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}
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class MuxGenerator(width: Int, nInput: Int) extends Module {
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require(width >= 0)
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require(nInput >= 1)
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125
npc/core/src/test/scala/Main.scala
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125
npc/core/src/test/scala/Main.scala
Normal file
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@ -0,0 +1,125 @@
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import chisel3._
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import chiseltest._
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import org.scalatest.freespec.AnyFreeSpec
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class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
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"RegisterFile should work" - {
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"with 2 read ports" in {
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test(new RegisterFile(2)) { c =>
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def readExpect(addr: Int, value: Int, port: Int = 0): Unit = {
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c.io.readAddr(port).poke(addr.U)
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c.io.readData(port).expect(value.U)
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}
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def write(addr: Int, value: Int): Unit = {
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c.io.writeEnable.poke(true.B)
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c.io.writeData.poke(value.U)
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c.io.writeAddr.poke(addr.U)
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c.clock.step(1)
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c.io.writeEnable.poke(false.B)
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}
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// everything should be 0 on init
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for (i <- 0 until 32) {
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readExpect(i, 0, port = 0)
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readExpect(i, 0, port = 1)
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}
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// write 5 * addr + 3
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for (i <- 0 until 32) {
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write(i, 5 * i + 3)
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}
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// check that the writes worked
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for (i <- 0 until 32) {
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readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2)
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}
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}
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}
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}
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}
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class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
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"With 32 width, " - {
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"add should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(0.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(8.U)
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}
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}
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"sub should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(1.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(2.U)
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}
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}
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"not should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(2.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect((-6).U)
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}
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}
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"and should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(3.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(1.U)
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}
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}
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"or should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(4.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(7.U)
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}
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}
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"xor should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(5.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(6.U)
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}
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}
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"compare should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(6)
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c.io.a.poke(62.U)
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c.io.b.poke(3.U)
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c.io.out.expect(0.U)
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c.io.a.poke(2.U)
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c.io.b.poke(103.U)
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c.io.out.expect(1.U)
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c.io.a.poke(16.U)
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c.io.b.poke(16.U)
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c.io.out.expect(1.U)
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}
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}
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"equal should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(7)
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c.io.a.poke(62.U)
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c.io.b.poke(3.U)
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c.io.out.expect(0.U)
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c.io.a.poke(2.U)
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c.io.b.poke(103.U)
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c.io.out.expect(0.U)
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c.io.a.poke(16.U)
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c.io.b.poke(16.U)
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c.io.out.expect(1.U)
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}
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}
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}
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}
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@ -1,71 +0,0 @@
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import chisel3._
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import chiseltest._
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import org.scalatest.freespec.AnyFreeSpec
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class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
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"RegisterFile should work" - {
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"with 2 read ports" in {
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test(new RegisterFile(2)) { c =>
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def readExpect(addr: Int, value: Int, port: Int = 0): Unit = {
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c.io.readAddr(port).poke(addr.U)
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c.io.readData(port).expect(value.U)
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}
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def write(addr: Int, value: Int): Unit = {
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c.io.writeEnable.poke(true.B)
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c.io.writeData.poke(value.U)
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c.io.writeAddr.poke(addr.U)
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c.clock.step(1)
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c.io.writeEnable.poke(false.B)
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}
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// everything should be 0 on init
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for (i <- 0 until 32) {
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readExpect(i, 0, port = 0)
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readExpect(i, 0, port = 1)
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}
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// write 5 * addr + 3
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for (i <- 0 until 32) {
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write(i, 5 * i + 3)
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}
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// check that the writes worked
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for (i <- 0 until 32) {
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readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2)
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}
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}
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}
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}
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}
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class MuxGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
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"MuxGenerator should work" - {
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"when there are 2 inputs" in {
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test(new MuxGenerator(8, 2)) { c =>
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c.io.in(0).poke(0.U)
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c.io.in(1).poke(1.U)
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c.io.sel.poke(0.U)
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c.io.out.expect(0.U)
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c.io.sel.poke(1.U)
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c.io.out.expect(1.U)
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}
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}
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"when there are 1024 inputs" in {
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test(new MuxGenerator(32, 1024)) { c =>
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for (i <- 0 until 1024) {
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c.io.in(i).poke(i.U)
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}
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for (i <- 0 until 1024) {
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c.io.sel.poke(i.U)
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c.io.out.expect(i.U)
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}
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}
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}
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}
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"MuxGenerator should raise exception" - {
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"when nInput is not 2^n" in {
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assertThrows[IllegalArgumentException] {
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test(new MuxGenerator(8, 3)) { c => }
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}
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}
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}
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}
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