> compile NEMU
ysyx_22040000 李心杨 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar 1 12:35:11 UTC 2024 x86_64 GNU/Linux 15:34:03 up 5:10, 2 users, load average: 0.44, 0.29, 0.40
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19 changed files with 208 additions and 406 deletions
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@ -1,47 +1,105 @@
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package flow
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package npc
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import chisel3._
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import chiseltest._
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import org.scalatest.freespec.AnyFreeSpec
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import chiseltest.simulator.WriteVcdAnnotation
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import flow.Flow
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import npc.util._
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class RV32CPUSpec extends AnyFreeSpec with ChiselScalatestTester {
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"MemoryFile" - {
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"correctly load" in {
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import chisel3.util.{SRAM, SRAMInterface, HexMemoryFile}
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class UserMem extends Module {
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val io = IO(new SRAMInterface(1024, UInt(32.W), 1, 1, 0))
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val memoryFile = HexMemoryFile("../resource/addi.txt")
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io :<>= SRAM(
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size = 1024,
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tpe = UInt(32.W),
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numReadPorts = 1,
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numWritePorts = 1,
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numReadwritePorts = 0,
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memoryFile = memoryFile
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)
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val read = io.readPorts(0).data
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printf(cf"memoryFile=$memoryFile, readPort=$read%x\n")
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}
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test(new UserMem).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
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c.io.readPorts(0).enable.poke(true.B)
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c.io.writePorts(0).enable.poke(false.B)
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c.io.writePorts(0).address.poke(0.U)
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c.io.writePorts(0).data.poke(0.U)
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for (i <- 0 until 32) {
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c.io.readPorts(0).address.poke(i.U)
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class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
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"RegisterFile should work" - {
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"with 2 read ports" in {
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test(new RegisterFile(2)) { c =>
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def readExpect(addr: Int, value: Int, port: Int = 0): Unit = {
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c.io.readAddr(port).poke(addr.U)
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c.io.readData(port).expect(value.U)
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}
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def write(addr: Int, value: Int): Unit = {
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c.io.writeEnable.poke(true.B)
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c.io.writeData.poke(value.U)
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c.io.writeAddr.poke(addr.U)
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c.clock.step(1)
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c.io.writeEnable.poke(false.B)
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}
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// everything should be 0 on init
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for (i <- 0 until 32) {
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readExpect(i, 0, port = 0)
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readExpect(i, 0, port = 1)
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}
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// write 5 * addr + 3
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for (i <- 0 until 32) {
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write(i, 5 * i + 3)
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}
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// check that the writes worked
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for (i <- 0 until 32) {
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readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2)
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}
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}
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}
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}
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"should compile" in {
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test(new Flow) { c =>
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c.clock.step(1)
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}
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class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
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"With 32 width, " - {
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val neg = (x: BigInt) => BigInt("FFFFFFFF", 16) - x + 1
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val not = (x: BigInt) => x ^ BigInt("FFFFFFFF", 16)
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val mask = BigInt("FFFFFFFF", 16)
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val oprands: List[(BigInt, BigInt)] = List(
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(5, 3), (101010, 101010), (0xFFFFFFFCL, 0xFFFFFFFFL), (4264115, 2)
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)
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val operations: Map[Int, (BigInt, BigInt) => BigInt] = Map(
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0 -> ((a: BigInt, b: BigInt) => (a + b) & mask),
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1 -> ((a: BigInt, b: BigInt) => (a + neg(b)) & mask),
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2 -> ((a, _) => not(a)),
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3 -> (_ & _),
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4 -> (_ | _),
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5 -> (_ ^ _),
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6 -> ((a, b) => if (a < b) 1 else 0),
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7 -> ((a, b) => if (a == b) 1 else 0),
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)
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val validate = (c: ALUGenerator,op: Int, oprands: List[(BigInt, BigInt)]) => {
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c.io.op.poke(op.U)
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oprands.foreach({ case (a, b) =>
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c.io.a.poke(a.U)
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c.io.b.poke(b.U)
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c.io.out.expect(operations(op)(a, b))
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})
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}
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"add should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 0, oprands) }
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}
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"sub should work" - {
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"with positive result" in {
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test(new ALUGenerator(32)) { c =>
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validate(c, 1, oprands.filter({case (a, b) => a >= b}))
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}
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}
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"with negative result" in {
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test(new ALUGenerator(32)) { c =>
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validate(c, 1, oprands.filter({case (a, b) => a < b}))
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}
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}
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}
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"not should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 2, oprands) }
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}
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"and should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 3, oprands) }
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}
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"or should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 4, oprands) }
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}
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"xor should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 5, oprands) }
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}
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"compare should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 6, oprands) }
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}
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"equal should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 7, oprands) }
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}
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}
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}
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@ -1,11 +1,11 @@
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package flow
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package flowpc
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import chisel3._
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import chiseltest._
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import org.scalatest.freespec.AnyFreeSpec
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import chiseltest.simulator.WriteVcdAnnotation
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import flow.components._
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import flowpc.components._
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class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
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"RegisterFileCore" - {
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"register 0 is always 0" in {
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}
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}
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"RegisterInterface" - {
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class Top extends Module {
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val io = IO(new RegFileInterface(32, UInt(32.W), 2, 2))
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val rf = RegisterFile(32, UInt(32.W), 2, 2)
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io :<>= rf
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}
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"write" in {
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test(new Top).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
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import c.io.control.WriteSelect._
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val writePort = rAluOut.litValue.toInt
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c.io.control.writeEnable.poke(true)
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c.io.control.writeSelect.poke(rAluOut)
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c.io.in.writeAddr.poke(5)
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c.io.in.writeData(writePort).poke(0xcdef)
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c.io.in.rs(0).poke(5)
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c.clock.step(1)
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c.io.out.src(0).expect(0xcdef)
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"worked" in {
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class Top extends Module {
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val io = IO(new RegFileInterface(32, UInt(32.W), 2, 2))
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val rf = RegisterFile(32, UInt(32.W), 2, 2)
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io :<>= rf
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}
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}
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"no data is written when not enabled" in {
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test(new Top).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
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import c.io.control.WriteSelect._
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val writePort = rAluOut.litValue.toInt
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c.io.control.writeEnable.poke(true)
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c.io.control.writeSelect.poke(rAluOut)
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c.io.in.writeAddr.poke(5)
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c.io.in.writeData(writePort).poke(0xcdef)
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c.io.in.rs(0).poke(5)
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c.io.data.write.addr.poke(5)
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c.io.data.write.data(writePort).poke(0xcdef)
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c.io.data.read(0).rs.poke(5)
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c.clock.step(1)
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c.io.control.writeEnable.poke(false)
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c.io.in.writeData(writePort).poke(0x1234)
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c.clock.step(1)
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c.io.out.src(0).expect(0xcdef)
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c.io.data.read(0).src.expect(0xcdef)
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}
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}
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}
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