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> compile NEMU

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ysyx_22040000 李心杨
Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar  1 12:35:11 UTC 2024 x86_64 GNU/Linux
 15:34:03  up   5:10,  2 users,  load average: 0.44, 0.29, 0.40
This commit is contained in:
tracer-ysyx 2024-03-13 15:34:03 +08:00 • committed by xinyangli
parent b5f076e957
commit 18d33c363b
19 changed files with 208 additions and 406 deletions
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122
npc/core/src/test/scala/Main.scala
View file

@ -1,47 +1,105 @@
package flow
package npc
import chisel3._
import chiseltest._
import org.scalatest.freespec.AnyFreeSpec
import chiseltest.simulator.WriteVcdAnnotation
import flow.Flow
import npc.util._
class RV32CPUSpec extends AnyFreeSpec with ChiselScalatestTester {
"MemoryFile" - {
"correctly load" in {
import chisel3.util.{SRAM, SRAMInterface, HexMemoryFile}
class UserMem extends Module {
val io = IO(new SRAMInterface(1024, UInt(32.W), 1, 1, 0))
val memoryFile = HexMemoryFile("../resource/addi.txt")
io :<>= SRAM(
size = 1024,
tpe = UInt(32.W),
numReadPorts = 1,
numWritePorts = 1,
numReadwritePorts = 0,
memoryFile = memoryFile
)
val read = io.readPorts(0).data
printf(cf"memoryFile=$memoryFile, readPort=$read%x\n")
}
test(new UserMem).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
c.io.readPorts(0).enable.poke(true.B)
c.io.writePorts(0).enable.poke(false.B)
c.io.writePorts(0).address.poke(0.U)
c.io.writePorts(0).data.poke(0.U)
for (i <- 0 until 32) {
c.io.readPorts(0).address.poke(i.U)
class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
"RegisterFile should work" - {
"with 2 read ports" in {
test(new RegisterFile(2)) { c =>
def readExpect(addr: Int, value: Int, port: Int = 0): Unit = {
c.io.readAddr(port).poke(addr.U)
c.io.readData(port).expect(value.U)
}
def write(addr: Int, value: Int): Unit = {
c.io.writeEnable.poke(true.B)
c.io.writeData.poke(value.U)
c.io.writeAddr.poke(addr.U)
c.clock.step(1)
c.io.writeEnable.poke(false.B)
}
// everything should be 0 on init
for (i <- 0 until 32) {
readExpect(i, 0, port = 0)
readExpect(i, 0, port = 1)
}
// write 5 * addr + 3
for (i <- 0 until 32) {
write(i, 5 * i + 3)
}
// check that the writes worked
for (i <- 0 until 32) {
readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2)
}
}
}
}
"should compile" in {
test(new Flow) { c =>
c.clock.step(1)
}
class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
"With 32 width, " - {
val neg = (x: BigInt) => BigInt("FFFFFFFF", 16) - x + 1
val not = (x: BigInt) => x ^ BigInt("FFFFFFFF", 16)
val mask = BigInt("FFFFFFFF", 16)
val oprands: List[(BigInt, BigInt)] = List(
(5, 3), (101010, 101010), (0xFFFFFFFCL, 0xFFFFFFFFL), (4264115, 2)
)
val operations: Map[Int, (BigInt, BigInt) => BigInt] = Map(
0 -> ((a: BigInt, b: BigInt) => (a + b) & mask),
1 -> ((a: BigInt, b: BigInt) => (a + neg(b)) & mask),
2 -> ((a, _) => not(a)),
3 -> (_ & _),
4 -> (_ | _),
5 -> (_ ^ _),
6 -> ((a, b) => if (a < b) 1 else 0),
7 -> ((a, b) => if (a == b) 1 else 0),
)
val validate = (c: ALUGenerator,op: Int, oprands: List[(BigInt, BigInt)]) => {
c.io.op.poke(op.U)
oprands.foreach({ case (a, b) =>
c.io.a.poke(a.U)
c.io.b.poke(b.U)
c.io.out.expect(operations(op)(a, b))
})
}
"add should work" in {
test(new ALUGenerator(32)) { c => validate(c, 0, oprands) }
}
"sub should work" - {
"with positive result" in {
test(new ALUGenerator(32)) { c =>
validate(c, 1, oprands.filter({case (a, b) => a >= b}))
}
}
"with negative result" in {
test(new ALUGenerator(32)) { c =>
validate(c, 1, oprands.filter({case (a, b) => a < b}))
}
}
}
"not should work" in {
test(new ALUGenerator(32)) { c => validate(c, 2, oprands) }
}
"and should work" in {
test(new ALUGenerator(32)) { c => validate(c, 3, oprands) }
}
"or should work" in {
test(new ALUGenerator(32)) { c => validate(c, 4, oprands) }
}
"xor should work" in {
test(new ALUGenerator(32)) { c => validate(c, 5, oprands) }
}
"compare should work" in {
test(new ALUGenerator(32)) { c => validate(c, 6, oprands) }
}
"equal should work" in {
test(new ALUGenerator(32)) { c => validate(c, 7, oprands) }
}
}
}

40
npc/core/src/test/scala/RegisterFile.scala
View file

@ -1,11 +1,11 @@
package flow
package flowpc
import chisel3._
import chiseltest._
import org.scalatest.freespec.AnyFreeSpec
import chiseltest.simulator.WriteVcdAnnotation
import flow.components._
import flowpc.components._
class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
"RegisterFileCore" - {
"register 0 is always 0" in {
@ -41,40 +41,22 @@ class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
}
}
"RegisterInterface" - {
class Top extends Module {
val io = IO(new RegFileInterface(32, UInt(32.W), 2, 2))
val rf = RegisterFile(32, UInt(32.W), 2, 2)
io :<>= rf
}
"write" in {
test(new Top).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
import c.io.control.WriteSelect._
val writePort = rAluOut.litValue.toInt
c.io.control.writeEnable.poke(true)
c.io.control.writeSelect.poke(rAluOut)
c.io.in.writeAddr.poke(5)
c.io.in.writeData(writePort).poke(0xcdef)
c.io.in.rs(0).poke(5)
c.clock.step(1)
c.io.out.src(0).expect(0xcdef)
"worked" in {
class Top extends Module {
val io = IO(new RegFileInterface(32, UInt(32.W), 2, 2))
val rf = RegisterFile(32, UInt(32.W), 2, 2)
io :<>= rf
}
}
"no data is written when not enabled" in {
test(new Top).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
import c.io.control.WriteSelect._
val writePort = rAluOut.litValue.toInt
c.io.control.writeEnable.poke(true)
c.io.control.writeSelect.poke(rAluOut)
c.io.in.writeAddr.poke(5)
c.io.in.writeData(writePort).poke(0xcdef)
c.io.in.rs(0).poke(5)
c.io.data.write.addr.poke(5)
c.io.data.write.data(writePort).poke(0xcdef)
c.io.data.read(0).rs.poke(5)
c.clock.step(1)
c.io.control.writeEnable.poke(false)
c.io.in.writeData(writePort).poke(0x1234)
c.clock.step(1)
c.io.out.src(0).expect(0xcdef)
c.io.data.read(0).src.expect(0xcdef)
}
}
}