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build: move to cmake

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xinyangli 2024-01-05 23:50:26 +08:00
parent 38818f6f66
commit 1702da0a0a
11 changed files with 896 additions and 78 deletions
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85
npc/Makefile
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@ -1,28 +1,56 @@
NVBOARD_HOME ?= $(abspath ../nvboard)
PREFIX ?= build
OBJDIR := $(PREFIX)/obj
TARGET := $(OBJDIR)/Vexample
CHISEL_VDIR := $(PREFIX)/chisel
VSRC := $(wildcard vsrc/*.v)
CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
SUBMAKE := $(OBJDIR)/Vexample.mk
VERILATOR_FLAGS := --cc --exe
LDFLAGS += $(shell sdl2-config --libs) -lSDL2_image
all: sim-bin nvboard-bin
$(OBJDIR)/Vexample: $(SUBMAKE)
$(MAKE) -C $(OBJDIR) -f $(notdir $(SUBMAKE)) Vexample
CHISEL_TOP_PACKAGE := learning
CHISEL_TOP_MODULE := Main
CHISEL_TARGET := verilog
$(SUBMAKE): $(VSRC) $(CPPSRCS) $(OBJDIR)
verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(VSRC) $(CPPSRCS)
SUBDIRS := obj nvobj
SUBDIRS := $(addprefix $(PREFIX),$(SUBDIRS))
SUBMAKE := $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
# Pretty printing
MAKEFLAGS += --no-print-directory
GREEN := \e[32m
NC := \e[0m
define colorize
printf '$(GREEN)'$(1)'$(NC) $(2)\n'
endef
all: sim-bin nvboard-bin
$(SUBDIRS):%: %/V$(CHISEL_TOP_MODULE).mk
verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(CHISEL_VSRC) $(CPPSRCS)
$(OBJDIR)/V$(CHISEL_TOP_MODULE): $(SUBMAKE)
@$(call colorize,"SUBMAKE",$^)
$(MAKE) -s -C $(dir $@) -f $< $(notdir $@)
$(SUBMAKE): $(CPPSRCS) $(OBJDIR) chisel-src
@$(call colorize,"VERILATOR",$@)
verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(CHISEL_VSRC) $(CPPSRCS)
$(OBJDIR):
mkdir -p $(OBJDIR)
mkdir -p $@
sim-bin: VERILATOR_FLAGS += --trace
sim-bin: $(VSRC) $(CPPSRCS) $(OBJDIR)/Vexample
$(CHISEL_VDIR)/filelist.f: $(wildcard src/main/scala/*.scala)
@$(call colorize,"CIRCT",$^)
sbt --error "runMain circt.stage.ChiselMain --module $(CHISEL_TOP_PACKAGE).$(CHISEL_TOP_MODULE) --split-verilog --target $(CHISEL_TARGET) -td $(CHISEL_VDIR)"
compile_commands.json: clean
$(MAKE) $(CHISEL_VDIR)/filelist.f
$(RM) compile_commands.json
bear --append -- $(MAKE) nvboard-bin
bear --append -- $(MAKE) sim-bin
.PHONY: clean nvboard sim nvboard-bin sim-bin git_trace_sim git_trace_nvboard
SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp)
NXDC_FILES := $(abspath constr/top.nxdc)
@ -30,13 +58,19 @@ $(SRC_AUTO_BIND): $(NXDC_FILES)
NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@
nvboard-bin: OBJDIR := $(PREFIX)/nvobj
nvboard-bin: SUBMAKE := $(OBJDIR)/Vexample.mk
nvboard-bin: SUBMAKE := $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
# TODO: fix this awkward way to find nvboard.a
nvboard-bin: CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a
nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags) -g
nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags)
nvboard-bin: $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
@echo $(SUBMAKE) $(OBJDIR)
nvboard-bin: $(VSRC) $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/Vexample
sim-bin: VERILATOR_FLAGS += --trace
sim-bin: $(CPPSRCS) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
chisel-src: $(CHISEL_VDIR)/filelist.f
$(eval CHISEL_VSRC := $(wildcard $(CHISEL_VDIR)/*.sv))
@echo "GENERATED: $(CHISEL_VSRC)"
ifneq (,$(wildcard ../Makefile))
include ../Makefile
@ -51,21 +85,18 @@ git_trace_sim:
git_trace_nvboard:
$(call git_commit, "nvboard")
.PHONY: clean nvboard sim compile_commands.json
nvboard: OBJDIR := $(PREFIX)/nvobj
nvboard: nvboard-bin git_trace_nvboard
@NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/Vexample
@echo "Running NVBoard ..."
@echo "================================"
@NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
sim: sim-bin git_trace_sim
@echo "Running" $(OBJDIR)/Vexample "..."
@echo "Running verilator sim ..."
@echo "================================"
@$(OBJDIR)/Vexample
compile_commands.json: clean
bear --output nvboard.json -- $(MAKE) nvboard-bin
bear --output all.json -- $(MAKE) sim-bin
jq -s ".[0] + .[1]" all.json nvboard.json > compile_commands.json
$(RM) all.json nvboard.json
@$(OBJDIR)/V$(CHISEL_TOP_MODULE)
clean:
$(RM) -r $(PREFIX)
$(V).SILENT: