Add ps/2 keyboard module
This commit is contained in:
parent
0b34b19bdf
commit
1118f64668
14 changed files with 405 additions and 207 deletions
34
npc/core/src/main/scala/ALU.scala
Normal file
34
npc/core/src/main/scala/ALU.scala
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
package npc.util
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
class ALUGenerator(width: Int) extends Module {
|
||||
require(width >= 0)
|
||||
val io = IO(new Bundle {
|
||||
val a = Input(UInt(width.W))
|
||||
val b = Input(UInt(width.W))
|
||||
val op = Input(UInt(4.W))
|
||||
val out = Output(UInt(width.W))
|
||||
})
|
||||
|
||||
val adder_b = (Fill(width, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub
|
||||
val add = io.a + adder_b
|
||||
val and = io.a & io.b
|
||||
val not = ~io.a
|
||||
val or = io.a | io.b
|
||||
val xor = io.a ^ io.b
|
||||
val slt = io.a < io.b
|
||||
val eq = io.a === io.b
|
||||
|
||||
io.out := MuxLookup(io.op, 0.U)(Seq(
|
||||
0.U -> add,
|
||||
1.U -> add, // add with b reversed
|
||||
2.U -> not,
|
||||
3.U -> and,
|
||||
4.U -> or,
|
||||
5.U -> xor,
|
||||
6.U -> slt,
|
||||
7.U -> eq,
|
||||
))
|
||||
}
|
||||
55
npc/core/src/main/scala/Keyboard.scala
Normal file
55
npc/core/src/main/scala/Keyboard.scala
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
package npc.util
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util.{Counter, Decoupled, Queue, Reverse, MuxLookup}
|
||||
|
||||
class PS2Port extends Bundle {
|
||||
val clk = Input(Bool())
|
||||
val data = Input(UInt(1.W))
|
||||
}
|
||||
|
||||
object PS2Port {
|
||||
def apply(): PS2Port = {
|
||||
new PS2Port
|
||||
}
|
||||
}
|
||||
|
||||
class KeyboardController extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val ps2 = PS2Port()
|
||||
val out = Decoupled(UInt(8.W))
|
||||
})
|
||||
// valid only on the clock negedge of ps2_clk
|
||||
val ps2_clk_valid = RegNext(io.ps2.clk, false.B) & ~io.ps2.clk
|
||||
val cycle_counter = Counter(11)
|
||||
val concated_data = RegInit(0.U(8.W))
|
||||
|
||||
val queue_in = Wire(Flipped(Decoupled(UInt(8.W))))
|
||||
val queue = Queue(queue_in, entries = 8)
|
||||
val received = RegInit(Bool(), false.B)
|
||||
val pushed = RegNext(queue_in.valid && queue_in.ready, false.B)
|
||||
queue_in.valid := false.B
|
||||
queue_in.bits := Reverse(concated_data)
|
||||
io.out <> queue
|
||||
|
||||
when(cycle_counter.value === 0.U) {
|
||||
concated_data := 0.U
|
||||
received := false.B
|
||||
}
|
||||
|
||||
when(ps2_clk_valid) {
|
||||
when(cycle_counter.value < 9.U && cycle_counter.value >= 1.U) {
|
||||
concated_data := (concated_data << 1) | io.ps2.data
|
||||
}.elsewhen(cycle_counter.value === 9.U) {
|
||||
received := true.B
|
||||
}
|
||||
cycle_counter.inc()
|
||||
}
|
||||
|
||||
when(!pushed && received) {
|
||||
queue_in.valid := true.B
|
||||
}.elsewhen(pushed && received) {
|
||||
queue_in.valid := false.B
|
||||
received := false.B
|
||||
}
|
||||
}
|
||||
|
|
@ -4,113 +4,6 @@ import chisel3._
|
|||
import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
|
||||
import chisel3.stage.ChiselOption
|
||||
|
||||
class RegisterFile(readPorts: Int) extends Module {
|
||||
require(readPorts >= 0)
|
||||
val io = IO(new Bundle {
|
||||
val writeEnable = Input(Bool())
|
||||
val writeAddr = Input(UInt(5.W))
|
||||
val writeData = Input(UInt(32.W))
|
||||
val readAddr = Input(Vec(readPorts, UInt(5.W)))
|
||||
val readData = Output(Vec(readPorts, UInt(32.W)))
|
||||
})
|
||||
|
||||
val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W))))
|
||||
for (i <- 1 until 32) {
|
||||
regFile(i) := regFile(i)
|
||||
}
|
||||
regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr))
|
||||
regFile(0) := 0.U
|
||||
|
||||
for (i <- 0 until readPorts) {
|
||||
io.readData(i) := regFile(io.readAddr(i))
|
||||
}
|
||||
}
|
||||
|
||||
class ALUGenerator(width: Int) extends Module {
|
||||
require(width >= 0)
|
||||
val io = IO(new Bundle {
|
||||
val a = Input(UInt(width.W))
|
||||
val b = Input(UInt(width.W))
|
||||
val op = Input(UInt(4.W))
|
||||
val out = Output(UInt(width.W))
|
||||
})
|
||||
|
||||
val adder_b = (Fill(width, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub
|
||||
val add = io.a + adder_b
|
||||
val and = io.a & io.b
|
||||
val not = ~io.a
|
||||
val or = io.a | io.b
|
||||
val xor = io.a ^ io.b
|
||||
val slt = io.a < io.b
|
||||
val eq = io.a === io.b
|
||||
|
||||
io.out := MuxLookup(io.op, 0.U)(Seq(
|
||||
0.U -> add,
|
||||
1.U -> add, // add with b reversed
|
||||
2.U -> not,
|
||||
3.U -> and,
|
||||
4.U -> or,
|
||||
5.U -> xor,
|
||||
6.U -> slt,
|
||||
7.U -> eq,
|
||||
))
|
||||
}
|
||||
|
||||
class Test extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val in = Input(UInt(32.W))
|
||||
val out = Output(UInt(32.W))
|
||||
})
|
||||
|
||||
val regFile = Module(new RegisterFile(2))
|
||||
regFile.io.writeEnable := true.B
|
||||
regFile.io.writeAddr := 1.U
|
||||
regFile.io.writeData := io.in
|
||||
regFile.io.readAddr(0) := 0.U
|
||||
regFile.io.readAddr(1) := 1.U
|
||||
io.out := regFile.io.readData(1)
|
||||
}
|
||||
|
||||
class KeyboardController extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val ps2_clk = Input(Bool())
|
||||
val ps2_data = Input(UInt(1.W))
|
||||
val out = Decoupled(UInt(8.W))
|
||||
})
|
||||
val queue_io = Wire(Flipped(Decoupled(UInt(8.W))))
|
||||
queue_io.valid := true.B
|
||||
queue_io.bits := 0.B
|
||||
val queue = Queue(queue_io, entries = 8)
|
||||
io.out <> queue
|
||||
|
||||
// valid only on the clock negedge of ps2_clk
|
||||
val ps2_clk_valid = RegNext(io.ps2_clk, false.B) & ~io.ps2_clk
|
||||
val cycle_counter = Counter(11)
|
||||
val concated_data = RegInit(0.U(8.W))
|
||||
val is_receiving = RegInit(Bool(), false.B)
|
||||
|
||||
when(io.ps2_clk && io.ps2_data === 1.U) {
|
||||
// Start receiving data
|
||||
is_receiving := true.B
|
||||
}
|
||||
|
||||
when(is_receiving && ps2_clk_valid) {
|
||||
cycle_counter.inc()
|
||||
when(cycle_counter.value < 9.U && cycle_counter.value > 0.U) {
|
||||
concated_data := (concated_data << 1) | io.ps2_data
|
||||
}
|
||||
when(cycle_counter.value === 10.U) {
|
||||
is_receiving := false.B
|
||||
}
|
||||
}
|
||||
|
||||
when(is_receiving) {
|
||||
queue_io.noenq()
|
||||
}.otherwise{
|
||||
queue_io.enq(Reverse(concated_data))
|
||||
}
|
||||
}
|
||||
|
||||
class Switch extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val sw = Input(Vec(2, Bool()))
|
||||
|
|
@ -119,3 +12,22 @@ class Switch extends Module {
|
|||
|
||||
io.out := io.sw(0) ^ io.sw(1)
|
||||
}
|
||||
|
||||
import npc.util.{PS2Port, KeyboardController, SegGenerator}
|
||||
|
||||
class Keyboard extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val ps2 = PS2Port()
|
||||
val segs = Output(Vec(8, UInt(8.W)))
|
||||
})
|
||||
|
||||
val seg_handler = Module(new SegGenerator(seg_count = 8))
|
||||
val keyboard_controller = Module(new KeyboardController)
|
||||
|
||||
seg_handler.io.keycode <> keyboard_controller.io.out
|
||||
|
||||
keyboard_controller.io.ps2 := io.ps2
|
||||
io.segs := seg_handler.io.segs
|
||||
}
|
||||
|
||||
class SegHandler extends SegGenerator(8) { }
|
||||
|
|
|
|||
25
npc/core/src/main/scala/RegisterFile.scala
Normal file
25
npc/core/src/main/scala/RegisterFile.scala
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
package npc.util
|
||||
|
||||
import chisel3._
|
||||
|
||||
class RegisterFile(readPorts: Int) extends Module {
|
||||
require(readPorts >= 0)
|
||||
val io = IO(new Bundle {
|
||||
val writeEnable = Input(Bool())
|
||||
val writeAddr = Input(UInt(5.W))
|
||||
val writeData = Input(UInt(32.W))
|
||||
val readAddr = Input(Vec(readPorts, UInt(5.W)))
|
||||
val readData = Output(Vec(readPorts, UInt(32.W)))
|
||||
})
|
||||
|
||||
val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W))))
|
||||
for (i <- 1 until 32) {
|
||||
regFile(i) := regFile(i)
|
||||
}
|
||||
regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr))
|
||||
regFile(0) := 0.U
|
||||
|
||||
for (i <- 0 until readPorts) {
|
||||
io.readData(i) := regFile(io.readAddr(i))
|
||||
}
|
||||
}
|
||||
48
npc/core/src/main/scala/SegGenerator.scala
Normal file
48
npc/core/src/main/scala/SegGenerator.scala
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
package npc.util
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import chisel3.util.log2Ceil
|
||||
|
||||
class SegGenerator(seg_count: Int) extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val keycode = Flipped(Decoupled(UInt(8.W)))
|
||||
val segs = Output(Vec(seg_count, UInt(8.W)))
|
||||
})
|
||||
io.keycode.ready := false.B
|
||||
when(io.keycode.valid) {
|
||||
io.keycode.ready := true.B
|
||||
}
|
||||
|
||||
val seg_regs = RegInit(VecInit(Seq.fill(seg_count)(0.U(8.W))))
|
||||
val last_keycode = RegInit(0.U(8.W))
|
||||
val digit_to_seg = ((0 until 16).map(_.U)).zip(Seq(
|
||||
"b00000011".U, "b10011111".U, "b00100101".U, "b00001101".U,
|
||||
"b10011001".U, "b01001001".U, "b01000001".U, "b00011111".U,
|
||||
"b00000001".U, "b00001001".U, "b00010001".U, "b11000001".U,
|
||||
"b01100011".U, "b10000101".U, "b01100001".U, "b01110001".U,
|
||||
))
|
||||
|
||||
val keycode_to_ascii = Seq(
|
||||
0x1C.U, 0x32.U, 0x21.U, 0x23.U, 0x24.U, 0x2B.U,
|
||||
0x34.U, 0x33.U, 0x43.U, 0x3B.U, 0x42.U, 0x4B.U,
|
||||
0x3A.U, 0x31.U, 0x44.U, 0x4D.U, 0x15.U, 0x2D.U,
|
||||
0x1B.U, 0x2C.U, 0x3C.U, 0x2A.U, 0x1D.U, 0x22.U,
|
||||
0x35.U, 0x1A.U, 0x45.U, 0x16.U, 0x1E.U, 0x26.U,
|
||||
0x25.U, 0x2E.U, 0x36.U, 0x3D.U, 0x3E.U, 0x46.U,
|
||||
).zip(((0x41 to 0x5A) ++ (0x30 to 0x39)).map(_.U))
|
||||
|
||||
val keycode = RegEnable(io.keycode.bits, io.keycode.ready && io.keycode.valid)
|
||||
val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4))
|
||||
val keycode_seg = keycode_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
|
||||
val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii)
|
||||
val ascii_digits = VecInit(ascii(3,0)) ++ VecInit(ascii(6,4))
|
||||
val ascii_seg = ascii_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
|
||||
val (counter, _) = Counter(io.keycode.valid && io.keycode.ready && io.keycode.bits =/= keycode, 0xFF)
|
||||
val count_digits = VecInit(counter(3,0)) ++ VecInit(counter(7,4))
|
||||
val count_seg = count_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
|
||||
|
||||
seg_regs := keycode_seg ++ ascii_seg ++ count_seg ++ Seq(0xFF.U, 0xFF.U)
|
||||
|
||||
io.segs := seg_regs
|
||||
}
|
||||
72
npc/core/src/test/scala/Keyboard.scala
Normal file
72
npc/core/src/test/scala/Keyboard.scala
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
package npc.keyboard
|
||||
|
||||
import chisel3._
|
||||
import chiseltest._
|
||||
import org.scalatest.freespec.AnyFreeSpec
|
||||
import chiseltest.simulator.WriteVcdAnnotation
|
||||
|
||||
import npc.util._
|
||||
|
||||
class KeyboardControllerSpec extends AnyFreeSpec with ChiselScalatestTester {
|
||||
def transfer(keycode: Int, clock: Clock, ps2: PS2Port) : Unit = {
|
||||
require(keycode >= 0 && keycode < 0xFF)
|
||||
var cycle = 0
|
||||
var keycode_remain = keycode << 1 // Shift 1 to do nothing at cycle 0
|
||||
var keycode_collect = 0
|
||||
|
||||
ps2.data.poke(1)
|
||||
ps2.clk.poke(true)
|
||||
clock.step(1)
|
||||
for (cycle <- 0 until 9) {
|
||||
val last_digit = keycode_remain & 1
|
||||
ps2.clk.poke(true)
|
||||
ps2.data.poke(last_digit)
|
||||
clock.step(32)
|
||||
keycode_collect = keycode_collect | (last_digit << cycle)
|
||||
keycode_remain = keycode_remain >> 1
|
||||
ps2.clk.poke(false)
|
||||
clock.step(32)
|
||||
}
|
||||
for (_ <- 9 until 11) {
|
||||
ps2.clk.poke(true)
|
||||
clock.step(32)
|
||||
ps2.clk.poke(false)
|
||||
clock.step(32)
|
||||
}
|
||||
assert(keycode_collect >> 1 == keycode)
|
||||
clock.step(32)
|
||||
}
|
||||
"Simple test" in {
|
||||
test(new KeyboardController).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
|
||||
val data = Array(0xE4, 0xD4, 0xC4, 0xA9)
|
||||
data.foreach(d => {
|
||||
transfer(d, c.clock, c.io.ps2)
|
||||
c.io.out.valid.expect(1.U)
|
||||
c.io.out.bits.expect(d)
|
||||
c.io.out.ready.poke(1)
|
||||
c.clock.step(1)
|
||||
c.io.out.ready.poke(0)
|
||||
})
|
||||
data.foreach(d => {
|
||||
transfer(d, c.clock, c.io.ps2)
|
||||
})
|
||||
data.foreach(d => {
|
||||
c.io.out.valid.expect(1.U)
|
||||
c.io.out.bits.expect(d)
|
||||
c.io.out.ready.poke(1)
|
||||
c.clock.step(1)
|
||||
c.io.out.ready.poke(0)
|
||||
})
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
class SegSpec extends AnyFreeSpec with ChiselScalatestTester {
|
||||
"try out vec" in {
|
||||
test(new SegGenerator(8)) {c =>
|
||||
c.io.keycode.bits.poke(0xAC)
|
||||
c.clock.step(1)
|
||||
println(s"out: ${c.io.segs(0).peek().litValue}")
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -3,9 +3,10 @@ package npc
|
|||
import chisel3._
|
||||
import chiseltest._
|
||||
import org.scalatest.freespec.AnyFreeSpec
|
||||
import chiseltest.simulator.ChiselBridge
|
||||
import chiseltest.simulator.WriteVcdAnnotation
|
||||
|
||||
import npc.util._
|
||||
|
||||
class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
|
||||
"RegisterFile should work" - {
|
||||
"with 2 read ports" in {
|
||||
|
|
@ -102,46 +103,3 @@ class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
class KeyboardControllerSpec extends AnyFreeSpec with ChiselScalatestTester {
|
||||
def transfer(keycode: Int, c: KeyboardController) : Unit = {
|
||||
require(keycode >= 0 && keycode < 0xFF)
|
||||
var cycle = 0
|
||||
var ps2_clk = true
|
||||
var keycode_remain = keycode << 1 // Shift 1 to do nothing at cycle 1
|
||||
var keycode_collect = 0
|
||||
|
||||
c.io.ps2_clk.poke(ps2_clk)
|
||||
c.io.ps2_data.poke(1)
|
||||
for (cycle <- 0 until 9) {
|
||||
c.io.ps2_clk.poke(true)
|
||||
c.clock.step(32)
|
||||
val last_digit = keycode_remain & 1
|
||||
c.io.ps2_data.poke(last_digit)
|
||||
keycode_collect = keycode_collect | (last_digit << cycle)
|
||||
keycode_remain = keycode_remain >> 1
|
||||
c.io.ps2_clk.poke(false)
|
||||
c.clock.step(32)
|
||||
}
|
||||
for (_ <- 9 until 11) {
|
||||
c.io.ps2_clk.poke(true)
|
||||
c.clock.step(32)
|
||||
c.io.ps2_clk.poke(ps2_clk)
|
||||
ps2_clk = !ps2_clk
|
||||
c.io.ps2_clk.poke(false)
|
||||
c.clock.step(32)
|
||||
}
|
||||
assert(keycode_collect >> 1 == keycode)
|
||||
c.io.out.ready.poke(1)
|
||||
c.clock.step(32)
|
||||
c.io.out.bits.expect(keycode)
|
||||
}
|
||||
"Simple test" in {
|
||||
test(new KeyboardController).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
|
||||
transfer(0xE4, c)
|
||||
transfer(0xE4, c)
|
||||
transfer(0xE4, c)
|
||||
transfer(0xE4, c)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue