implement keyboard controller
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a2986aab78
commit
0b34b19bdf
8 changed files with 284 additions and 237 deletions
121
npc/core/src/main/scala/Main.scala
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121
npc/core/src/main/scala/Main.scala
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@ -0,0 +1,121 @@
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package npc
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import chisel3._
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import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
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import chisel3.stage.ChiselOption
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class RegisterFile(readPorts: Int) extends Module {
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require(readPorts >= 0)
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val io = IO(new Bundle {
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val writeEnable = Input(Bool())
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val writeAddr = Input(UInt(5.W))
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val writeData = Input(UInt(32.W))
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val readAddr = Input(Vec(readPorts, UInt(5.W)))
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val readData = Output(Vec(readPorts, UInt(32.W)))
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})
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val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W))))
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for (i <- 1 until 32) {
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regFile(i) := regFile(i)
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}
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regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr))
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regFile(0) := 0.U
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for (i <- 0 until readPorts) {
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io.readData(i) := regFile(io.readAddr(i))
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}
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}
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class ALUGenerator(width: Int) extends Module {
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require(width >= 0)
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val io = IO(new Bundle {
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val a = Input(UInt(width.W))
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val b = Input(UInt(width.W))
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val op = Input(UInt(4.W))
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val out = Output(UInt(width.W))
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})
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val adder_b = (Fill(width, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub
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val add = io.a + adder_b
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val and = io.a & io.b
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val not = ~io.a
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val or = io.a | io.b
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val xor = io.a ^ io.b
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val slt = io.a < io.b
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val eq = io.a === io.b
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io.out := MuxLookup(io.op, 0.U)(Seq(
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0.U -> add,
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1.U -> add, // add with b reversed
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2.U -> not,
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3.U -> and,
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4.U -> or,
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5.U -> xor,
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6.U -> slt,
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7.U -> eq,
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))
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}
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class Test extends Module {
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val io = IO(new Bundle {
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val in = Input(UInt(32.W))
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val out = Output(UInt(32.W))
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})
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val regFile = Module(new RegisterFile(2))
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regFile.io.writeEnable := true.B
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regFile.io.writeAddr := 1.U
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regFile.io.writeData := io.in
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regFile.io.readAddr(0) := 0.U
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regFile.io.readAddr(1) := 1.U
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io.out := regFile.io.readData(1)
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}
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class KeyboardController extends Module {
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val io = IO(new Bundle {
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val ps2_clk = Input(Bool())
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val ps2_data = Input(UInt(1.W))
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val out = Decoupled(UInt(8.W))
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})
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val queue_io = Wire(Flipped(Decoupled(UInt(8.W))))
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queue_io.valid := true.B
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queue_io.bits := 0.B
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val queue = Queue(queue_io, entries = 8)
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io.out <> queue
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// valid only on the clock negedge of ps2_clk
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val ps2_clk_valid = RegNext(io.ps2_clk, false.B) & ~io.ps2_clk
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val cycle_counter = Counter(11)
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val concated_data = RegInit(0.U(8.W))
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val is_receiving = RegInit(Bool(), false.B)
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when(io.ps2_clk && io.ps2_data === 1.U) {
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// Start receiving data
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is_receiving := true.B
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}
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when(is_receiving && ps2_clk_valid) {
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cycle_counter.inc()
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when(cycle_counter.value < 9.U && cycle_counter.value > 0.U) {
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concated_data := (concated_data << 1) | io.ps2_data
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}
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when(cycle_counter.value === 10.U) {
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is_receiving := false.B
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}
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}
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when(is_receiving) {
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queue_io.noenq()
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}.otherwise{
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queue_io.enq(Reverse(concated_data))
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}
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}
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class Switch extends Module {
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val io = IO(new Bundle {
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val sw = Input(Vec(2, Bool()))
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val out = Output(Bool())
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})
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io.out := io.sw(0) ^ io.sw(1)
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}
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@ -1,64 +0,0 @@
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package npc
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import chisel3._
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import chisel3.stage.ChiselOption
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class RegisterFile(readPorts: Int) extends Module {
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require(readPorts >= 0)
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val io = IO(new Bundle {
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val writeEnable = Input(Bool())
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val writeAddr = Input(UInt(5.W))
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val writeData = Input(UInt(32.W))
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val readAddr = Input(Vec(readPorts, UInt(5.W)))
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val readData = Output(Vec(readPorts, UInt(32.W)))
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})
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val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W))))
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for (i <- 1 until 32) {
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regFile(i) := regFile(i)
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}
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regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr))
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regFile(0) := 0.U
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for (i <- 0 until readPorts) {
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io.readData(i) := regFile(io.readAddr(i))
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}
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}
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class MuxGenerator(width: Int, nInput: Int) extends Module {
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require(width >= 0)
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require(nInput >= 1)
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require(nInput.toBinaryString.map(_ - '0').sum == 1)
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val io = IO(new Bundle {
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val in = Input(Vec(nInput, UInt(width.W)))
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val sel = Input(UInt(nInput.toBinaryString.reverse.indexOf('1').W))
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val out = Output(UInt(width.W))
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})
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io.out := io.in(io.sel)
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}
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class Test extends Module {
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val io = IO(new Bundle {
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val in = Input(UInt(32.W))
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val out = Output(UInt(32.W))
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})
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val regFile = Module(new RegisterFile(2))
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regFile.io.writeEnable := true.B
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regFile.io.writeAddr := 1.U
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regFile.io.writeData := io.in
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regFile.io.readAddr(0) := 0.U
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regFile.io.readAddr(1) := 1.U
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io.out := regFile.io.readData(1)
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}
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class Switch extends Module {
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val io = IO(new Bundle {
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val sw = Input(Vec(2, Bool()))
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val out = Output(Bool())
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})
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io.out := io.sw(0) ^ io.sw(1)
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}
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