implement keyboard controller
This commit is contained in:
parent
a2986aab78
commit
0b34b19bdf
8 changed files with 284 additions and 237 deletions
13
npc/core/.gitignore
vendored
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13
npc/core/.gitignore
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# Created by https://www.toptal.com/developers/gitignore/api/scala
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# Edit at https://www.toptal.com/developers/gitignore?templates=scala
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### Scala ###
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*.class
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*.log
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# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
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hs_err_pid*
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# End of https://www.toptal.com/developers/gitignore/api/scala
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test_run_dir/
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2
npc/core/.scalafmt.conf
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2
npc/core/.scalafmt.conf
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version = "3.7.15"
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runner.dialect = scala213
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121
npc/core/src/main/scala/Main.scala
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121
npc/core/src/main/scala/Main.scala
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package npc
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import chisel3._
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import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
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import chisel3.stage.ChiselOption
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class RegisterFile(readPorts: Int) extends Module {
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require(readPorts >= 0)
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val io = IO(new Bundle {
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val writeEnable = Input(Bool())
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val writeAddr = Input(UInt(5.W))
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val writeData = Input(UInt(32.W))
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val readAddr = Input(Vec(readPorts, UInt(5.W)))
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val readData = Output(Vec(readPorts, UInt(32.W)))
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})
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val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W))))
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for (i <- 1 until 32) {
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regFile(i) := regFile(i)
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}
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regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr))
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regFile(0) := 0.U
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for (i <- 0 until readPorts) {
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io.readData(i) := regFile(io.readAddr(i))
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}
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}
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class ALUGenerator(width: Int) extends Module {
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require(width >= 0)
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val io = IO(new Bundle {
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val a = Input(UInt(width.W))
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val b = Input(UInt(width.W))
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val op = Input(UInt(4.W))
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val out = Output(UInt(width.W))
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})
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val adder_b = (Fill(width, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub
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val add = io.a + adder_b
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val and = io.a & io.b
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val not = ~io.a
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val or = io.a | io.b
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val xor = io.a ^ io.b
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val slt = io.a < io.b
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val eq = io.a === io.b
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io.out := MuxLookup(io.op, 0.U)(Seq(
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0.U -> add,
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1.U -> add, // add with b reversed
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2.U -> not,
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3.U -> and,
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4.U -> or,
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5.U -> xor,
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6.U -> slt,
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7.U -> eq,
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))
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}
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class Test extends Module {
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val io = IO(new Bundle {
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val in = Input(UInt(32.W))
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val out = Output(UInt(32.W))
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})
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val regFile = Module(new RegisterFile(2))
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regFile.io.writeEnable := true.B
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regFile.io.writeAddr := 1.U
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regFile.io.writeData := io.in
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regFile.io.readAddr(0) := 0.U
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regFile.io.readAddr(1) := 1.U
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io.out := regFile.io.readData(1)
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}
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class KeyboardController extends Module {
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val io = IO(new Bundle {
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val ps2_clk = Input(Bool())
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val ps2_data = Input(UInt(1.W))
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val out = Decoupled(UInt(8.W))
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})
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val queue_io = Wire(Flipped(Decoupled(UInt(8.W))))
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queue_io.valid := true.B
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queue_io.bits := 0.B
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val queue = Queue(queue_io, entries = 8)
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io.out <> queue
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// valid only on the clock negedge of ps2_clk
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val ps2_clk_valid = RegNext(io.ps2_clk, false.B) & ~io.ps2_clk
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val cycle_counter = Counter(11)
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val concated_data = RegInit(0.U(8.W))
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val is_receiving = RegInit(Bool(), false.B)
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when(io.ps2_clk && io.ps2_data === 1.U) {
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// Start receiving data
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is_receiving := true.B
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}
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when(is_receiving && ps2_clk_valid) {
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cycle_counter.inc()
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when(cycle_counter.value < 9.U && cycle_counter.value > 0.U) {
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concated_data := (concated_data << 1) | io.ps2_data
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}
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when(cycle_counter.value === 10.U) {
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is_receiving := false.B
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}
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}
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when(is_receiving) {
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queue_io.noenq()
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}.otherwise{
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queue_io.enq(Reverse(concated_data))
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}
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}
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class Switch extends Module {
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val io = IO(new Bundle {
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val sw = Input(Vec(2, Bool()))
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val out = Output(Bool())
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})
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io.out := io.sw(0) ^ io.sw(1)
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}
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@ -1,64 +0,0 @@
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package npc
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import chisel3._
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import chisel3.stage.ChiselOption
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class RegisterFile(readPorts: Int) extends Module {
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require(readPorts >= 0)
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val io = IO(new Bundle {
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val writeEnable = Input(Bool())
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val writeAddr = Input(UInt(5.W))
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val writeData = Input(UInt(32.W))
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val readAddr = Input(Vec(readPorts, UInt(5.W)))
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val readData = Output(Vec(readPorts, UInt(32.W)))
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})
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val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W))))
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for (i <- 1 until 32) {
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regFile(i) := regFile(i)
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}
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regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr))
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regFile(0) := 0.U
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for (i <- 0 until readPorts) {
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io.readData(i) := regFile(io.readAddr(i))
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}
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}
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class MuxGenerator(width: Int, nInput: Int) extends Module {
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require(width >= 0)
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require(nInput >= 1)
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require(nInput.toBinaryString.map(_ - '0').sum == 1)
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val io = IO(new Bundle {
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val in = Input(Vec(nInput, UInt(width.W)))
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val sel = Input(UInt(nInput.toBinaryString.reverse.indexOf('1').W))
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val out = Output(UInt(width.W))
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})
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io.out := io.in(io.sel)
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}
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class Test extends Module {
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val io = IO(new Bundle {
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val in = Input(UInt(32.W))
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val out = Output(UInt(32.W))
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})
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val regFile = Module(new RegisterFile(2))
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regFile.io.writeEnable := true.B
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regFile.io.writeAddr := 1.U
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regFile.io.writeData := io.in
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regFile.io.readAddr(0) := 0.U
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regFile.io.readAddr(1) := 1.U
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io.out := regFile.io.readData(1)
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}
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class Switch extends Module {
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val io = IO(new Bundle {
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val sw = Input(Vec(2, Bool()))
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val out = Output(Bool())
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})
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io.out := io.sw(0) ^ io.sw(1)
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}
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147
npc/core/src/test/scala/Main.scala
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147
npc/core/src/test/scala/Main.scala
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package npc
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import chisel3._
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import chiseltest._
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import org.scalatest.freespec.AnyFreeSpec
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import chiseltest.simulator.ChiselBridge
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import chiseltest.simulator.WriteVcdAnnotation
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class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
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"RegisterFile should work" - {
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"with 2 read ports" in {
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test(new RegisterFile(2)) { c =>
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def readExpect(addr: Int, value: Int, port: Int = 0): Unit = {
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c.io.readAddr(port).poke(addr.U)
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c.io.readData(port).expect(value.U)
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}
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def write(addr: Int, value: Int): Unit = {
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c.io.writeEnable.poke(true.B)
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c.io.writeData.poke(value.U)
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c.io.writeAddr.poke(addr.U)
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c.clock.step(1)
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c.io.writeEnable.poke(false.B)
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}
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// everything should be 0 on init
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for (i <- 0 until 32) {
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readExpect(i, 0, port = 0)
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readExpect(i, 0, port = 1)
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}
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// write 5 * addr + 3
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for (i <- 0 until 32) {
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write(i, 5 * i + 3)
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}
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// check that the writes worked
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for (i <- 0 until 32) {
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readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2)
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}
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}
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}
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}
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}
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class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
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"With 32 width, " - {
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val neg = (x: BigInt) => BigInt("FFFFFFFF", 16) - x + 1
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val not = (x: BigInt) => x ^ BigInt("FFFFFFFF", 16)
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val mask = BigInt("FFFFFFFF", 16)
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val oprands: List[(BigInt, BigInt)] = List(
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(5, 3), (101010, 101010), (0xFFFFFFFCL, 0xFFFFFFFFL), (4264115, 2)
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)
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val operations: Map[Int, (BigInt, BigInt) => BigInt] = Map(
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0 -> ((a: BigInt, b: BigInt) => (a + b) & mask),
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1 -> ((a: BigInt, b: BigInt) => (a + neg(b)) & mask),
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2 -> ((a, _) => not(a)),
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3 -> (_ & _),
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4 -> (_ | _),
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5 -> (_ ^ _),
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6 -> ((a, b) => if (a < b) 1 else 0),
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7 -> ((a, b) => if (a == b) 1 else 0),
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)
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val validate = (c: ALUGenerator,op: Int, oprands: List[(BigInt, BigInt)]) => {
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c.io.op.poke(op.U)
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oprands.foreach({ case (a, b) =>
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c.io.a.poke(a.U)
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c.io.b.poke(b.U)
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c.io.out.expect(operations(op)(a, b))
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})
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}
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"add should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 0, oprands) }
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}
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"sub should work" - {
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"with positive result" in {
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test(new ALUGenerator(32)) { c =>
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validate(c, 1, oprands.filter({case (a, b) => a >= b}))
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}
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}
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"with negative result" in {
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test(new ALUGenerator(32)) { c =>
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validate(c, 1, oprands.filter({case (a, b) => a < b}))
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}
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}
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}
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"not should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 2, oprands) }
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}
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"and should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 3, oprands) }
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}
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"or should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 4, oprands) }
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}
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"xor should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 5, oprands) }
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}
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"compare should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 6, oprands) }
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}
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"equal should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 7, oprands) }
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}
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}
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}
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class KeyboardControllerSpec extends AnyFreeSpec with ChiselScalatestTester {
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def transfer(keycode: Int, c: KeyboardController) : Unit = {
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require(keycode >= 0 && keycode < 0xFF)
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var cycle = 0
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var ps2_clk = true
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var keycode_remain = keycode << 1 // Shift 1 to do nothing at cycle 1
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var keycode_collect = 0
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c.io.ps2_clk.poke(ps2_clk)
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c.io.ps2_data.poke(1)
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for (cycle <- 0 until 9) {
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c.io.ps2_clk.poke(true)
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c.clock.step(32)
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val last_digit = keycode_remain & 1
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c.io.ps2_data.poke(last_digit)
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keycode_collect = keycode_collect | (last_digit << cycle)
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keycode_remain = keycode_remain >> 1
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c.io.ps2_clk.poke(false)
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c.clock.step(32)
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}
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for (_ <- 9 until 11) {
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c.io.ps2_clk.poke(true)
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c.clock.step(32)
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c.io.ps2_clk.poke(ps2_clk)
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ps2_clk = !ps2_clk
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c.io.ps2_clk.poke(false)
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c.clock.step(32)
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}
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assert(keycode_collect >> 1 == keycode)
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c.io.out.ready.poke(1)
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c.clock.step(32)
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c.io.out.bits.expect(keycode)
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}
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"Simple test" in {
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test(new KeyboardController).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
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transfer(0xE4, c)
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transfer(0xE4, c)
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transfer(0xE4, c)
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transfer(0xE4, c)
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}
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}
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}
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@ -1,71 +0,0 @@
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import chisel3._
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import chiseltest._
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import org.scalatest.freespec.AnyFreeSpec
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class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
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"RegisterFile should work" - {
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"with 2 read ports" in {
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test(new RegisterFile(2)) { c =>
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def readExpect(addr: Int, value: Int, port: Int = 0): Unit = {
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c.io.readAddr(port).poke(addr.U)
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c.io.readData(port).expect(value.U)
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}
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def write(addr: Int, value: Int): Unit = {
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c.io.writeEnable.poke(true.B)
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c.io.writeData.poke(value.U)
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c.io.writeAddr.poke(addr.U)
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c.clock.step(1)
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c.io.writeEnable.poke(false.B)
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}
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// everything should be 0 on init
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for (i <- 0 until 32) {
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readExpect(i, 0, port = 0)
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readExpect(i, 0, port = 1)
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}
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// write 5 * addr + 3
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for (i <- 0 until 32) {
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write(i, 5 * i + 3)
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}
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// check that the writes worked
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for (i <- 0 until 32) {
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readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2)
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}
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}
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}
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}
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}
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class MuxGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
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"MuxGenerator should work" - {
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"when there are 2 inputs" in {
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test(new MuxGenerator(8, 2)) { c =>
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c.io.in(0).poke(0.U)
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c.io.in(1).poke(1.U)
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c.io.sel.poke(0.U)
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c.io.out.expect(0.U)
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c.io.sel.poke(1.U)
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c.io.out.expect(1.U)
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}
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}
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"when there are 1024 inputs" in {
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test(new MuxGenerator(32, 1024)) { c =>
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for (i <- 0 until 1024) {
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c.io.in(i).poke(i.U)
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}
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for (i <- 0 until 1024) {
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c.io.sel.poke(i.U)
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c.io.out.expect(i.U)
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}
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}
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}
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}
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"MuxGenerator should raise exception" - {
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"when nInput is not 2^n" in {
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assertThrows[IllegalArgumentException] {
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test(new MuxGenerator(8, 3)) { c => }
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}
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}
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}
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}
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