import RT-Thread@9217865c without bsp, libcpu and components/net
This commit is contained in:
Zihao Yu
commit
e2376a3709
1414 changed files with 390370 additions and 0 deletions
28
components/lwp/arch/aarch64/common/reloc.c
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28
components/lwp/arch/aarch64/common/reloc.c
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@ -0,0 +1,28 @@
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#include <rtthread.h>
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#include <stdint.h>
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#include <string.h>
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#include <elf.h>
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#ifdef ARCH_MM_MMU
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#include <mmu.h>
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#include <page.h>
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#endif
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#define Elf_Word Elf64_Word
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#define Elf_Addr Elf64_Addr
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#define Elf_Half Elf64_Half
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#define Elf_Ehdr Elf64_Ehdr #define Elf_Phdr Elf64_Phdr
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#define Elf_Shdr Elf64_Shdr
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typedef struct
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{
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Elf_Word st_name;
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Elf_Addr st_value;
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Elf_Word st_size;
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unsigned char st_info;
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unsigned char st_other;
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Elf_Half st_shndx;
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} Elf_sym;
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void arch_elf_reloc(void *text_start, void *rel_dyn_start, size_t rel_dyn_size, void *got_start, size_t got_size, Elf_sym *dynsym)
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{
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}
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94
components/lwp/arch/aarch64/cortex-a/lwp_arch.c
Normal file
94
components/lwp/arch/aarch64/cortex-a/lwp_arch.c
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@ -0,0 +1,94 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-05-18 Jesven first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#ifdef ARCH_MM_MMU
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#define DBG_TAG "lwp.arch"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#include <lwp_arch.h>
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#include <lwp_user_mm.h>
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extern size_t MMUTable[];
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int arch_user_space_init(struct rt_lwp *lwp)
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{
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size_t *mmu_table;
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mmu_table = (size_t *)rt_pages_alloc_ext(0, PAGE_ANY_AVAILABLE);
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if (!mmu_table)
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{
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return -RT_ENOMEM;
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}
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lwp->end_heap = USER_HEAP_VADDR;
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memset(mmu_table, 0, ARCH_PAGE_SIZE);
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_table, ARCH_PAGE_SIZE);
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lwp->aspace = rt_aspace_create(
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(void *)USER_VADDR_START, USER_VADDR_TOP - USER_VADDR_START, mmu_table);
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if (!lwp->aspace)
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{
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return -RT_ERROR;
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}
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return 0;
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}
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void *arch_kernel_mmu_table_get(void)
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{
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return (void *)NULL;
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}
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void arch_user_space_free(struct rt_lwp *lwp)
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{
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if (lwp)
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{
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RT_ASSERT(lwp->aspace);
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void *pgtbl = lwp->aspace->page_table;
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rt_aspace_delete(lwp->aspace);
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/* must be freed after aspace delete, pgtbl is required for unmap */
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rt_pages_free(pgtbl, 0);
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lwp->aspace = NULL;
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}
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else
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{
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LOG_W("%s: NULL lwp as parameter", __func__);
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RT_ASSERT(0);
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}
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}
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int arch_expand_user_stack(void *addr)
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{
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int ret = 0;
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size_t stack_addr = (size_t)addr;
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stack_addr &= ~ARCH_PAGE_MASK;
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if ((stack_addr >= (size_t)USER_STACK_VSTART) &&
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(stack_addr < (size_t)USER_STACK_VEND))
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{
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void *map =
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lwp_map_user(lwp_self(), (void *)stack_addr, ARCH_PAGE_SIZE, 0);
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if (map || lwp_user_accessable(addr, 1))
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{
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ret = 1;
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}
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}
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return ret;
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}
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#endif
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45
components/lwp/arch/aarch64/cortex-a/lwp_arch.h
Normal file
45
components/lwp/arch/aarch64/cortex-a/lwp_arch.h
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@ -0,0 +1,45 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-05-18 Jesven first version
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*/
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#ifndef LWP_ARCH_H__
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#define LWP_ARCH_H__
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#include <lwp.h>
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#include <lwp_arch_comm.h>
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#ifdef ARCH_MM_MMU
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#define USER_VADDR_TOP 0x0001000000000000UL
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#define USER_HEAP_VEND 0x0000ffffB0000000UL
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#define USER_HEAP_VADDR 0x0000ffff80000000UL
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#define USER_STACK_VSTART 0x0000ffff70000000UL
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#define USER_STACK_VEND USER_HEAP_VADDR
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#define LDSO_LOAD_VADDR 0x60000000UL
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#define USER_VADDR_START 0x00200000UL
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#define USER_LOAD_VADDR USER_VADDR_START
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#ifdef __cplusplus
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extern "C" {
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#endif
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unsigned long rt_hw_ffz(unsigned long x);
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rt_inline void icache_invalid_all(void)
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{
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asm volatile ("ic ialluis\n\tisb sy":::"memory");
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /*LWP_ARCH_H__*/
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593
components/lwp/arch/aarch64/cortex-a/lwp_gcc.S
Normal file
593
components/lwp/arch/aarch64/cortex-a/lwp_gcc.S
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@ -0,0 +1,593 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-05-18 Jesven first version
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*/
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#include "rtconfig.h"
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#include "asm-generic.h"
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#include "asm-fpu.h"
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/*********************
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* SPSR BIT *
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*********************/
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#define SPSR_Mode(v) ((v) << 0)
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#define SPSR_A64 (0 << 4)
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#define SPSR_RESEVRED_5 (0 << 5)
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#define SPSR_FIQ_MASKED(v) ((v) << 6)
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#define SPSR_IRQ_MASKED(v) ((v) << 7)
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#define SPSR_SERROR_MASKED(v) ((v) << 8)
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#define SPSR_D_MASKED(v) ((v) << 9)
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#define SPSR_RESEVRED_10_19 (0 << 10)
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#define SPSR_IL(v) ((v) << 20)
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#define SPSR_SS(v) ((v) << 21)
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#define SPSR_RESEVRED_22_27 (0 << 22)
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#define SPSR_V(v) ((v) << 28)
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#define SPSR_C(v) ((v) << 29)
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#define SPSR_Z(v) ((v) << 30)
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#define SPSR_N(v) ((v) << 31)
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/*********************
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* CONTEXT_OFFSET *
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*********************/
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#define CONTEXT_OFFSET_ELR_EL1 0x0
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#define CONTEXT_OFFSET_SPSR_EL1 0x8
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#define CONTEXT_OFFSET_SP_EL0 0x10
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#define CONTEXT_OFFSET_X30 0x18
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#define CONTEXT_OFFSET_FPCR 0x20
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#define CONTEXT_OFFSET_FPSR 0x28
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#define CONTEXT_OFFSET_X28 0x30
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#define CONTEXT_OFFSET_X29 0x38
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#define CONTEXT_OFFSET_X26 0x40
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#define CONTEXT_OFFSET_X27 0x48
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#define CONTEXT_OFFSET_X24 0x50
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#define CONTEXT_OFFSET_X25 0x58
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#define CONTEXT_OFFSET_X22 0x60
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#define CONTEXT_OFFSET_X23 0x68
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#define CONTEXT_OFFSET_X20 0x70
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#define CONTEXT_OFFSET_X21 0x78
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#define CONTEXT_OFFSET_X18 0x80
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#define CONTEXT_OFFSET_X19 0x88
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#define CONTEXT_OFFSET_X16 0x90
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#define CONTEXT_OFFSET_X17 0x98
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#define CONTEXT_OFFSET_X14 0xa0
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#define CONTEXT_OFFSET_X15 0xa8
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#define CONTEXT_OFFSET_X12 0xb0
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#define CONTEXT_OFFSET_X13 0xb8
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#define CONTEXT_OFFSET_X10 0xc0
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#define CONTEXT_OFFSET_X11 0xc8
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#define CONTEXT_OFFSET_X8 0xd0
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#define CONTEXT_OFFSET_X9 0xd8
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#define CONTEXT_OFFSET_X6 0xe0
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#define CONTEXT_OFFSET_X7 0xe8
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#define CONTEXT_OFFSET_X4 0xf0
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#define CONTEXT_OFFSET_X5 0xf8
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#define CONTEXT_OFFSET_X2 0x100
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#define CONTEXT_OFFSET_X3 0x108
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#define CONTEXT_OFFSET_X0 0x110
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#define CONTEXT_OFFSET_X1 0x118
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#define CONTEXT_OFFSET_Q15 0x120
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#define CONTEXT_OFFSET_Q14 0x130
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#define CONTEXT_OFFSET_Q13 0x140
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#define CONTEXT_OFFSET_Q12 0x150
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#define CONTEXT_OFFSET_Q11 0x160
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#define CONTEXT_OFFSET_Q10 0x170
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#define CONTEXT_OFFSET_Q9 0x180
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#define CONTEXT_OFFSET_Q8 0x190
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#define CONTEXT_OFFSET_Q7 0x1a0
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#define CONTEXT_OFFSET_Q6 0x1b0
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#define CONTEXT_OFFSET_Q5 0x1c0
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#define CONTEXT_OFFSET_Q4 0x1d0
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#define CONTEXT_OFFSET_Q3 0x1e0
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#define CONTEXT_OFFSET_Q2 0x1f0
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#define CONTEXT_OFFSET_Q1 0x200
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#define CONTEXT_OFFSET_Q0 0x210
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#define CONTEXT_FPU_SIZE 0x100
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#define CONTEXT_SIZE 0x220
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/**************************************************/
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.text
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/*
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* void arch_start_umode(args, text, ustack, kstack);
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*/
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.global arch_start_umode
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.type arch_start_umode, % function
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arch_start_umode:
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mov sp, x3
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mov x4, #(SPSR_Mode(0) | SPSR_A64)
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mov x3, x2 ;/* user stack top */
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msr daifset, #3
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dsb sy
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mrs x30, sp_el0
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msr spsr_el1, x4
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msr elr_el1, x1
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eret
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/*
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* void arch_crt_start_umode(args, text, ustack, kstack);
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*/
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.global arch_crt_start_umode
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.type arch_crt_start_umode, % function
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arch_crt_start_umode:
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sub x4, x2, #0x10
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adr x2, lwp_thread_return
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ldr x5, [x2]
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str x5, [x4]
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ldr x5, [x2, #4]
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str x5, [x4, #4]
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ldr x5, [x2, #8]
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str x5, [x4, #8]
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mov x5, x4
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dc cvau, x5
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add x5, x5, #8
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dc cvau, x5
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dsb sy
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ic ialluis
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dsb sy
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msr sp_el0, x4
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mov sp, x3
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mov x4, #(SPSR_Mode(0) | SPSR_A64)
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msr daifset, #3
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dsb sy
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mrs x30, sp_el0
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msr spsr_el1, x4
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msr elr_el1, x1
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eret
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/*
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void arch_set_thread_context(void *exit_addr, void *new_thread_stack, void *user_stack, void **thread_sp);
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*/
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.global arch_set_thread_context
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arch_set_thread_context:
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sub x1, x1, #CONTEXT_SIZE
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str x2, [x1, #CONTEXT_OFFSET_SP_EL0]
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sub x1, x1, #CONTEXT_SIZE
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str xzr, [x1, #CONTEXT_OFFSET_X0] /* new thread return 0 */
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mov x4, #((3 << 6) | 0x4 | 0x1) /* el1h, disable interrupt */
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str x4, [x1, #CONTEXT_OFFSET_SPSR_EL1]
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str x0, [x1, #CONTEXT_OFFSET_ELR_EL1]
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str x1, [x3]
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ret
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.global arch_get_user_sp
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arch_get_user_sp:
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mrs x0, sp_el0
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ret
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.global arch_fork_exit
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.global arch_clone_exit
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arch_fork_exit:
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arch_clone_exit:
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b arch_syscall_exit
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/*
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void lwp_exec_user(void *args, void *kernel_stack, void *user_entry)
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*/
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.global lwp_exec_user
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lwp_exec_user:
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mov sp, x1
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mov x4, #(SPSR_Mode(0) | SPSR_A64)
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ldr x3, =0x0000ffff80000000
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msr daifset, #3
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msr spsr_el1, x4
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msr elr_el1, x2
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eret
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/*
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* void SVC_Handler(regs);
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* since this routine reset the SP, we take it as a start point
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*/
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START_POINT(SVC_Handler)
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/* x0 is initial sp */
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mov sp, x0
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msr daifclr, #3 /* enable interrupt */
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bl rt_thread_self
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bl lwp_user_setting_save
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ldp x8, x9, [sp, #(CONTEXT_OFFSET_X8)]
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and x0, x8, #0xf000
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cmp x0, #0xe000
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beq arch_signal_quit
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cmp x0, #0xf000
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beq ret_from_user
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uxtb x0, w8
|
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bl lwp_get_sys_api
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cmp x0, xzr
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mov x30, x0
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beq arch_syscall_exit
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ldp x0, x1, [sp, #(CONTEXT_OFFSET_X0)]
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ldp x2, x3, [sp, #(CONTEXT_OFFSET_X2)]
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ldp x4, x5, [sp, #(CONTEXT_OFFSET_X4)]
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ldp x6, x7, [sp, #(CONTEXT_OFFSET_X6)]
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blr x30
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/* jump explictly, make this code position independant */
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b arch_syscall_exit
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START_POINT_END(SVC_Handler)
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.global arch_syscall_exit
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arch_syscall_exit:
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msr daifset, #3
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ldp x2, x3, [sp], #0x10 /* SPSR and ELR. */
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msr spsr_el1, x3
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msr elr_el1, x2
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|
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ldp x29, x30, [sp], #0x10
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msr sp_el0, x29
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ldp x28, x29, [sp], #0x10
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msr fpcr, x28
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msr fpsr, x29
|
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ldp x28, x29, [sp], #0x10
|
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ldp x26, x27, [sp], #0x10
|
||||
ldp x24, x25, [sp], #0x10
|
||||
ldp x22, x23, [sp], #0x10
|
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ldp x20, x21, [sp], #0x10
|
||||
ldp x18, x19, [sp], #0x10
|
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ldp x16, x17, [sp], #0x10
|
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ldp x14, x15, [sp], #0x10
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ldp x12, x13, [sp], #0x10
|
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ldp x10, x11, [sp], #0x10
|
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ldp x8, x9, [sp], #0x10
|
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add sp, sp, #0x40
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RESTORE_FPU sp
|
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|
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.global arch_ret_to_user
|
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arch_ret_to_user:
|
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SAVE_FPU sp
|
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stp x0, x1, [sp, #-0x10]!
|
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stp x2, x3, [sp, #-0x10]!
|
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stp x4, x5, [sp, #-0x10]!
|
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stp x6, x7, [sp, #-0x10]!
|
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stp x8, x9, [sp, #-0x10]!
|
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stp x10, x11, [sp, #-0x10]!
|
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stp x12, x13, [sp, #-0x10]!
|
||||
stp x14, x15, [sp, #-0x10]!
|
||||
stp x16, x17, [sp, #-0x10]!
|
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stp x18, x19, [sp, #-0x10]!
|
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stp x20, x21, [sp, #-0x10]!
|
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stp x22, x23, [sp, #-0x10]!
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stp x24, x25, [sp, #-0x10]!
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stp x26, x27, [sp, #-0x10]!
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stp x28, x29, [sp, #-0x10]!
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|
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mrs x0, fpcr
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mrs x1, fpsr
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stp x0, x1, [sp, #-0x10]!
|
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stp x29, x30, [sp, #-0x10]!
|
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|
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bl lwp_check_debug
|
||||
bl lwp_check_exit_request
|
||||
cbz w0, 1f
|
||||
mov x0, xzr
|
||||
b sys_exit
|
||||
1:
|
||||
ldr x0, =rt_dbg_ops
|
||||
ldr x0, [x0]
|
||||
cbz x0, 3f
|
||||
bl dbg_thread_in_debug
|
||||
mov x1, #(1 << 21)
|
||||
mrs x2, spsr_el1
|
||||
cbz w0, 2f
|
||||
orr x2, x2, x1
|
||||
msr spsr_el1, x2
|
||||
b 3f
|
||||
2:
|
||||
bic x2, x2, x1
|
||||
msr spsr_el1, x2
|
||||
3:
|
||||
bl lwp_signal_check
|
||||
cmp x0, xzr
|
||||
|
||||
ldp x29, x30, [sp], #0x10
|
||||
ldp x0, x1, [sp], #0x10
|
||||
msr fpcr, x0
|
||||
msr fpsr, x1
|
||||
|
||||
ldp x28, x29, [sp], #0x10
|
||||
ldp x26, x27, [sp], #0x10
|
||||
ldp x24, x25, [sp], #0x10
|
||||
ldp x22, x23, [sp], #0x10
|
||||
ldp x20, x21, [sp], #0x10
|
||||
ldp x18, x19, [sp], #0x10
|
||||
ldp x16, x17, [sp], #0x10
|
||||
ldp x14, x15, [sp], #0x10
|
||||
ldp x12, x13, [sp], #0x10
|
||||
ldp x10, x11, [sp], #0x10
|
||||
ldp x8, x9, [sp], #0x10
|
||||
ldp x6, x7, [sp], #0x10
|
||||
ldp x4, x5, [sp], #0x10
|
||||
ldp x2, x3, [sp], #0x10
|
||||
ldp x0, x1, [sp], #0x10
|
||||
RESTORE_FPU sp
|
||||
|
||||
bne user_do_signal
|
||||
|
||||
stp x0, x1, [sp, #-0x10]!
|
||||
ldr x0, =rt_dbg_ops
|
||||
ldr x0, [x0]
|
||||
cmp x0, xzr
|
||||
ldp x0, x1, [sp], #0x10
|
||||
beq 1f
|
||||
SAVE_FPU sp
|
||||
stp x0, x1, [sp, #-0x10]!
|
||||
stp x2, x3, [sp, #-0x10]!
|
||||
stp x4, x5, [sp, #-0x10]!
|
||||
stp x6, x7, [sp, #-0x10]!
|
||||
stp x8, x9, [sp, #-0x10]!
|
||||
stp x10, x11, [sp, #-0x10]!
|
||||
stp x12, x13, [sp, #-0x10]!
|
||||
stp x14, x15, [sp, #-0x10]!
|
||||
stp x16, x17, [sp, #-0x10]!
|
||||
stp x18, x19, [sp, #-0x10]!
|
||||
stp x20, x21, [sp, #-0x10]!
|
||||
stp x22, x23, [sp, #-0x10]!
|
||||
stp x24, x25, [sp, #-0x10]!
|
||||
stp x26, x27, [sp, #-0x10]!
|
||||
stp x28, x29, [sp, #-0x10]!
|
||||
mrs x0, fpcr
|
||||
mrs x1, fpsr
|
||||
stp x0, x1, [sp, #-0x10]!
|
||||
stp x29, x30, [sp, #-0x10]!
|
||||
mrs x0, elr_el1
|
||||
bl dbg_attach_req
|
||||
ldp x29, x30, [sp], #0x10
|
||||
ldp x0, x1, [sp], #0x10
|
||||
msr fpcr, x0
|
||||
msr fpsr, x1
|
||||
ldp x28, x29, [sp], #0x10
|
||||
ldp x26, x27, [sp], #0x10
|
||||
ldp x24, x25, [sp], #0x10
|
||||
ldp x22, x23, [sp], #0x10
|
||||
ldp x20, x21, [sp], #0x10
|
||||
ldp x18, x19, [sp], #0x10
|
||||
ldp x16, x17, [sp], #0x10
|
||||
ldp x14, x15, [sp], #0x10
|
||||
ldp x12, x13, [sp], #0x10
|
||||
ldp x10, x11, [sp], #0x10
|
||||
ldp x8, x9, [sp], #0x10
|
||||
ldp x6, x7, [sp], #0x10
|
||||
ldp x4, x5, [sp], #0x10
|
||||
ldp x2, x3, [sp], #0x10
|
||||
ldp x0, x1, [sp], #0x10
|
||||
RESTORE_FPU sp
|
||||
1:
|
||||
eret
|
||||
|
||||
/*
|
||||
struct rt_hw_exp_stack
|
||||
{
|
||||
unsigned long pc; 0
|
||||
unsigned long cpsr;
|
||||
unsigned long sp_el0; 0x10
|
||||
unsigned long x30;
|
||||
unsigned long fpcr; 0x20
|
||||
unsigned long fpsr;
|
||||
unsigned long x28; 0x30
|
||||
unsigned long x29;
|
||||
unsigned long x26; 0x40
|
||||
unsigned long x27;
|
||||
unsigned long x24; 0x50
|
||||
unsigned long x25;
|
||||
unsigned long x22; 0x60
|
||||
unsigned long x23;
|
||||
unsigned long x20; 0x70
|
||||
unsigned long x21;
|
||||
unsigned long x18; 0x80
|
||||
unsigned long x19;
|
||||
unsigned long x16; 0x90
|
||||
unsigned long x17;
|
||||
unsigned long x14; 0xa0
|
||||
unsigned long x15;
|
||||
unsigned long x12; 0xb0
|
||||
unsigned long x13;
|
||||
unsigned long x10; 0xc0
|
||||
unsigned long x11;
|
||||
unsigned long x8; 0xd0
|
||||
unsigned long x9;
|
||||
unsigned long x6; 0xe0
|
||||
unsigned long x7;
|
||||
unsigned long x4; 0xf0
|
||||
unsigned long x5;
|
||||
unsigned long x2; 0x100
|
||||
unsigned long x3;
|
||||
unsigned long x0; 0x110
|
||||
unsigned long x1;
|
||||
|
||||
unsigned long long fpu[16]; 0x120
|
||||
0x220 = 0x120 + 0x10 * 0x10
|
||||
};
|
||||
*/
|
||||
.global lwp_check_debug
|
||||
lwp_check_debug:
|
||||
ldr x0, =rt_dbg_ops
|
||||
ldr x0, [x0]
|
||||
cbnz x0, 1f
|
||||
ret
|
||||
1:
|
||||
stp x29, x30, [sp, #-0x10]!
|
||||
bl dbg_check_suspend
|
||||
cbz w0, lwp_check_debug_quit
|
||||
|
||||
mrs x2, sp_el0
|
||||
sub x2, x2, #0x10
|
||||
mov x3, x2
|
||||
msr sp_el0, x2
|
||||
ldr x0, =lwp_debugreturn
|
||||
ldr w1, [x0]
|
||||
str w1, [x2]
|
||||
ldr w1, [x0, #4]
|
||||
str w1, [x2, #4]
|
||||
|
||||
dc cvau, x2
|
||||
add x2, x2, #4
|
||||
dc cvau, x2
|
||||
|
||||
dsb sy
|
||||
isb sy
|
||||
|
||||
ic ialluis
|
||||
isb sy
|
||||
|
||||
mrs x0, elr_el1
|
||||
mrs x1, spsr_el1
|
||||
stp x0, x1, [sp, #-0x10]!
|
||||
msr elr_el1, x3 /* lwp_debugreturn */
|
||||
mov x1, #(SPSR_Mode(0) | SPSR_A64)
|
||||
orr x1, x1, #(1 << 21)
|
||||
msr spsr_el1, x1
|
||||
eret
|
||||
ret_from_user:
|
||||
/* sp_el0 += 16 for drop ins lwp_debugreturn */
|
||||
mrs x0, sp_el0
|
||||
add x0, x0, #0x10
|
||||
msr sp_el0, x0
|
||||
/* now is el1, sp is pos(empty) - sizeof(context) */
|
||||
mov x0, sp
|
||||
add x0, x0, #0x220
|
||||
mov sp, x0
|
||||
ldp x0, x1, [sp], #0x10 /* x1 is origin spsr_el1 */
|
||||
msr elr_el1, x0 /* x0 is origin elr_el1 */
|
||||
msr spsr_el1, x1
|
||||
lwp_check_debug_quit:
|
||||
ldp x29, x30, [sp], #0x10
|
||||
ret
|
||||
|
||||
arch_signal_quit:
|
||||
msr daifset, #3
|
||||
/*
|
||||
drop stack data
|
||||
*/
|
||||
add sp, sp, #CONTEXT_SIZE
|
||||
bl lwp_signal_restore
|
||||
/* x0 is user_ctx : ori sp, pc, cpsr */
|
||||
ldr x1, [x0]
|
||||
ldr x2, [x0, #8]
|
||||
ldr x3, [x0, #16]
|
||||
msr spsr_el1, x3
|
||||
msr elr_el1, x2
|
||||
add x1, x1, #16
|
||||
msr sp_el0, x1
|
||||
|
||||
msr spsel, #0
|
||||
|
||||
ldp x29, x30, [sp], #0x10
|
||||
ldp x28, x29, [sp], #0x10
|
||||
msr fpcr, x28
|
||||
msr fpsr, x29
|
||||
ldp x28, x29, [sp], #0x10
|
||||
ldp x26, x27, [sp], #0x10
|
||||
ldp x24, x25, [sp], #0x10
|
||||
ldp x22, x23, [sp], #0x10
|
||||
ldp x20, x21, [sp], #0x10
|
||||
ldp x18, x19, [sp], #0x10
|
||||
ldp x16, x17, [sp], #0x10
|
||||
ldp x14, x15, [sp], #0x10
|
||||
ldp x12, x13, [sp], #0x10
|
||||
ldp x10, x11, [sp], #0x10
|
||||
ldp x8, x9, [sp], #0x10
|
||||
ldp x6, x7, [sp], #0x10
|
||||
ldp x4, x5, [sp], #0x10
|
||||
ldp x2, x3, [sp], #0x10
|
||||
ldp x0, x1, [sp], #0x10
|
||||
RESTORE_FPU sp
|
||||
|
||||
msr spsel, #1
|
||||
|
||||
b arch_ret_to_user
|
||||
|
||||
user_do_signal:
|
||||
msr spsel, #0
|
||||
SAVE_FPU sp
|
||||
stp x0, x1, [sp, #-0x10]!
|
||||
stp x2, x3, [sp, #-0x10]!
|
||||
stp x4, x5, [sp, #-0x10]!
|
||||
stp x6, x7, [sp, #-0x10]!
|
||||
stp x8, x9, [sp, #-0x10]!
|
||||
stp x10, x11, [sp, #-0x10]!
|
||||
stp x12, x13, [sp, #-0x10]!
|
||||
stp x14, x15, [sp, #-0x10]!
|
||||
stp x16, x17, [sp, #-0x10]!
|
||||
stp x18, x19, [sp, #-0x10]!
|
||||
stp x20, x21, [sp, #-0x10]!
|
||||
stp x22, x23, [sp, #-0x10]!
|
||||
stp x24, x25, [sp, #-0x10]!
|
||||
stp x26, x27, [sp, #-0x10]!
|
||||
stp x28, x29, [sp, #-0x10]!
|
||||
mrs x28, fpcr
|
||||
mrs x29, fpsr
|
||||
stp x28, x29, [sp, #-0x10]!
|
||||
stp x29, x30, [sp, #-0x10]!
|
||||
|
||||
sub sp, sp, #0x10
|
||||
adr x0, lwp_sigreturn
|
||||
ldr w1, [x0]
|
||||
str w1, [sp]
|
||||
ldr w1, [x0, #4]
|
||||
str w1, [sp, #4]
|
||||
|
||||
mov x20, sp /* lwp_sigreturn */
|
||||
mov x0, sp
|
||||
|
||||
dc cvau, x0
|
||||
dsb sy
|
||||
ic ialluis
|
||||
dsb sy
|
||||
|
||||
msr spsel, #1
|
||||
|
||||
mrs x1, elr_el1
|
||||
mrs x2, spsr_el1
|
||||
bl lwp_signal_backup
|
||||
/* x0 is signal */
|
||||
mov x19, x0
|
||||
bl lwp_sighandler_get
|
||||
adds x1, x0, xzr
|
||||
mov x0, x19
|
||||
bne 1f
|
||||
mov x1, x20
|
||||
1:
|
||||
msr elr_el1, x1
|
||||
mov x30, x20
|
||||
eret
|
||||
|
||||
lwp_debugreturn:
|
||||
mov x8, 0xf000
|
||||
svc #0
|
||||
|
||||
lwp_sigreturn:
|
||||
mov x8, #0xe000
|
||||
svc #0
|
||||
|
||||
lwp_thread_return:
|
||||
mov x0, xzr
|
||||
mov x8, #0x01
|
||||
svc #0
|
||||
|
||||
.globl arch_get_tidr
|
||||
arch_get_tidr:
|
||||
mrs x0, tpidr_el0
|
||||
ret
|
||||
|
||||
.global arch_set_thread_area
|
||||
arch_set_thread_area:
|
||||
.globl arch_set_tidr
|
||||
arch_set_tidr:
|
||||
msr tpidr_el0, x0
|
||||
ret
|
||||
Loading…
Add table
Add a link
Reference in a new issue