add riscv32e-npc

am/src/platform/nemu/include/nemu.h

@@ -10,7 +10,7 @@
 # define nemu_trap(code) asm volatile ("int3" : :"a"(code))
 #elif defined(__ISA_MIPS32__)
 # define nemu_trap(code) asm volatile ("move $v0, %0; sdbbp" : :"r"(code))
-#elif defined(__ISA_RISCV32__) || defined(__ISA_RISCV64__)
+#elif defined(__riscv)
 # define nemu_trap(code) asm volatile("mv a0, %0; ebreak" : :"r"(code))
 #elif defined(__ISA_LOONGARCH32R__)
 # define nemu_trap(code) asm volatile("move $a0, %0; break 0" : :"r"(code))

am/src/riscv/nemu/cte.c

@@ -35,7 +35,11 @@ Context *kcontext(Area kstack, void (*entry)(void *), void *arg) {
 }
 
 void yield() {
+#ifdef __riscv_e
+  asm volatile("li a5, -1; ecall");
+#else
   asm volatile("li a7, -1; ecall");
+#endif
 }
 
 bool ienabled() {

am/src/riscv/nemu/trap.S

@@ -12,20 +12,30 @@
 #define XLEN  8
 #endif
 
-#define REGS(f) \
+#define REGS_LO16(f) \
       f( 1)       f( 3) f( 4) f( 5) f( 6) f( 7) f( 8) f( 9) \
-f(10) f(11) f(12) f(13) f(14) f(15) f(16) f(17) f(18) f(19) \
+f(10) f(11) f(12) f(13) f(14) f(15)
+#ifndef __riscv_e
+#define REGS_HI16(f) \
+                                    f(16) f(17) f(18) f(19) \
 f(20) f(21) f(22) f(23) f(24) f(25) f(26) f(27) f(28) f(29) \
 f(30) f(31)
+#define NR_REGS 32
+#else
+#define REGS_HI16(f)
+#define NR_REGS 16
+#endif
+
+#define REGS(f) REGS_LO16(f) REGS_HI16(f)
 
 #define PUSH(n) STORE concat(x, n), (n * XLEN)(sp);
 #define POP(n)  LOAD  concat(x, n), (n * XLEN)(sp);
 
-#define CONTEXT_SIZE  ((32 + 3 + 1) * XLEN)
+#define CONTEXT_SIZE  ((NR_REGS + 3 + 1) * XLEN)
 #define OFFSET_SP     ( 2 * XLEN)
-#define OFFSET_CAUSE  (32 * XLEN)
+#define OFFSET_CAUSE  ((NR_REGS + 0) * XLEN)
-#define OFFSET_STATUS (33 * XLEN)
+#define OFFSET_STATUS ((NR_REGS + 1) * XLEN)
-#define OFFSET_EPC    (34 * XLEN)
+#define OFFSET_EPC    ((NR_REGS + 2) * XLEN)
 
 .align 3
 .globl __am_asm_trap

am/src/riscv/npc/cte.c

@@ -1,4 +1,5 @@
 #include <am.h>
+#include <riscv/riscv.h>
 #include <klib.h>
 
 static Context* (*user_handler)(Event, Context*) = NULL;
@@ -34,7 +35,11 @@ Context *kcontext(Area kstack, void (*entry)(void *), void *arg) {
 }
 
 void yield() {
+#ifdef __riscv_e
+  asm volatile("li a5, -1; ecall");
+#else
   asm volatile("li a7, -1; ecall");
+#endif
 }
 
 bool ienabled() {

am/src/riscv/npc/ioe.c

@@ -6,7 +6,6 @@ void __am_timer_init();
 void __am_timer_rtc(AM_TIMER_RTC_T *);
 void __am_timer_uptime(AM_TIMER_UPTIME_T *);
 void __am_input_keybrd(AM_INPUT_KEYBRD_T *);
-void __am_timer_rtc(AM_TIMER_RTC_T *);
 
 static void __am_timer_config(AM_TIMER_CONFIG_T *cfg) { cfg->present = true; cfg->has_rtc = true; }
 static void __am_input_config(AM_INPUT_CONFIG_T *cfg) { cfg->present = true;  }

am/src/riscv/npc/trap.S

@@ -1,51 +1,66 @@
-
 #define concat_temp(x, y) x ## y
 #define concat(x, y) concat_temp(x, y)
 #define MAP(c, f) c(f)
 
-#define REGS(f) \
+#if __riscv_xlen == 32
+#define LOAD  lw
+#define STORE sw
+#define XLEN  4
+#else
+#define LOAD  ld
+#define STORE sd
+#define XLEN  8
+#endif
+
+#define REGS_LO16(f) \
       f( 1)       f( 3) f( 4) f( 5) f( 6) f( 7) f( 8) f( 9) \
-f(10) f(11) f(12) f(13) f(14) f(15) f(16) f(17) f(18) f(19) \
+f(10) f(11) f(12) f(13) f(14) f(15)
+#ifndef __riscv_e
+#define REGS_HI16(f) \
+                                    f(16) f(17) f(18) f(19) \
 f(20) f(21) f(22) f(23) f(24) f(25) f(26) f(27) f(28) f(29) \
 f(30) f(31)
+#define NR_REGS 32
+#else
+#define REGS_HI16(f)
+#define NR_REGS 16
+#endif
 
-#define PUSH(n) sd concat(x, n), (n * 8)(sp);
+#define REGS(f) REGS_LO16(f) REGS_HI16(f)
-#define POP(n)  ld concat(x, n), (n * 8)(sp);
 
-#define CONTEXT_SIZE ((32 + 3) * 8)
+#define PUSH(n) STORE concat(x, n), (n * XLEN)(sp);
-#define OFFSET_SP     ( 2 * 8)
+#define POP(n)  LOAD  concat(x, n), (n * XLEN)(sp);
-#define OFFSET_CAUSE  (32 * 8)
-#define OFFSET_STATUS (33 * 8)
-#define OFFSET_EPC    (34 * 8)
 
+#define CONTEXT_SIZE  ((NR_REGS + 3 + 1) * XLEN)
+#define OFFSET_SP     ( 2 * XLEN)
+#define OFFSET_CAUSE  ((NR_REGS + 0) * XLEN)
+#define OFFSET_STATUS ((NR_REGS + 1) * XLEN)
+#define OFFSET_EPC    ((NR_REGS + 2) * XLEN)
+
+.align 3
 .globl __am_asm_trap
 __am_asm_trap:
   addi sp, sp, -CONTEXT_SIZE
 
   MAP(REGS, PUSH)
 
-  mv t0, sp
-  addi t0, t0, CONTEXT_SIZE
-  sd t0, OFFSET_SP(sp)
-
   csrr t0, mcause
   csrr t1, mstatus
   csrr t2, mepc
 
-  sd t0, OFFSET_CAUSE(sp)
+  STORE t0, OFFSET_CAUSE(sp)
-  sd t1, OFFSET_STATUS(sp)
+  STORE t1, OFFSET_STATUS(sp)
-  sd t2, OFFSET_EPC(sp)
+  STORE t2, OFFSET_EPC(sp)
 
   mv a0, sp
   jal __am_irq_handle
 
-  ld t1, OFFSET_STATUS(sp)
+  LOAD t1, OFFSET_STATUS(sp)
-  ld t2, OFFSET_EPC(sp)
+  LOAD t2, OFFSET_EPC(sp)
   csrw mstatus, t1
   csrw mepc, t2
 
   MAP(REGS, POP)
 
   addi sp, sp, CONTEXT_SIZE
-
   mret

scripts/platform/npc.mk

@@ -1,5 +1,3 @@
-include $(AM_HOME)/scripts/isa/riscv.mk
-
 AM_SRCS := riscv/npc/start.S \
            riscv/npc/trm.c \
            riscv/npc/ioe.c \
@@ -11,7 +9,8 @@ AM_SRCS := riscv/npc/start.S \
            platform/dummy/mpe.c
 
 CFLAGS    += -fdata-sections -ffunction-sections
-LDFLAGS   += -T $(AM_HOME)/scripts/linker.ld --defsym=_pmem_start=0x80000000 --defsym=_entry_offset=0x0
+LDFLAGS   += -T $(AM_HOME)/scripts/linker.ld \
+						 --defsym=_pmem_start=0x80000000 --defsym=_entry_offset=0x0
 LDFLAGS   += --gc-sections -e _start
 CFLAGS += -DMAINARGS=\"$(mainargs)\"
 .PHONY: $(AM_HOME)/am/src/riscv/npc/trm.c

scripts/riscv32e-nemu.mk

@@ -0,0 +1,10 @@
+include $(AM_HOME)/scripts/isa/riscv.mk
+include $(AM_HOME)/scripts/platform/nemu.mk
+CFLAGS  += -DISA_H=\"riscv/riscv.h\"
+COMMON_CFLAGS += -march=rv32em_zicsr -mabi=ilp32e  # overwrite
+LDFLAGS       += -melf32lriscv                     # overwrite
+
+AM_SRCS += riscv/nemu/start.S \
+           riscv/nemu/cte.c \
+           riscv/nemu/trap.S \
+           riscv/nemu/vme.c

scripts/riscv32e-npc.mk

@@ -0,0 +1,4 @@
+include $(AM_HOME)/scripts/isa/riscv.mk
+include $(AM_HOME)/scripts/platform/npc.mk
+COMMON_CFLAGS += -march=rv32e_zicsr -mabi=ilp32e  # overwrite
+LDFLAGS       += -melf32lriscv                    # overwrite