feat: riscv64 linux support
This commit is contained in:
kingfish404
Zihao Yu
parent
0e37b47498
commit
a7b830fedd
5 changed files with 52 additions and 29 deletions
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@ -11,8 +11,10 @@ struct Context {
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uintptr_t ksp;
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void *vm_head;
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ucontext_t uc;
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#ifdef __x86_64__
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// skip the red zone of the stack frame, see the amd64 ABI manual for details
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uint8_t redzone[128];
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#endif
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};
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#ifdef __x86_64__
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@ -21,12 +23,21 @@ struct Context {
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#define GPR3 uc.uc_mcontext.gregs[REG_RDX]
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#define GPR4 uc.uc_mcontext.gregs[REG_RCX]
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#define GPRx uc.uc_mcontext.gregs[REG_RAX]
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#elif __aarch64__
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#elif defined(__aarch64__)
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#define GPR1 uc.uc_mcontext.regs[0]
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#define GPR2 uc.uc_mcontext.regs[1]
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#define GPR3 uc.uc_mcontext.regs[2]
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#define GPR4 uc.uc_mcontext.regs[3]
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#define GPRx uc.uc_mcontext.regs[0]
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#elif defined(__riscv)
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// FIXME: may be wrong
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#define GPR1 uc.uc_mcontext.__gregs[REG_A0]
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#define GPR2 uc.uc_mcontext.__gregs[REG_A0+1]
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#define GPR3 uc.uc_mcontext.__gregs[REG_A0+2]
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#define GPR4 uc.uc_mcontext.__gregs[REG_A0+3]
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#define GPRx uc.uc_mcontext.__gregs[REG_A0+4]
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#else
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#error Unsupported architecture
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#endif
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#undef __USE_GNU
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@ -21,7 +21,7 @@ static void irq_handle(Context *c) {
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if (thiscpu->ev.event == EVENT_ERROR) {
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printf("Unhandle signal '%s' at pc = %p, badaddr = %p, cause = 0x%x\n",
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thiscpu->ev.msg, REG_PC(&c->uc), thiscpu->ev.ref, thiscpu->ev.cause);
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thiscpu->ev.msg, AM_REG_PC(&c->uc), thiscpu->ev.ref, thiscpu->ev.cause);
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assert(0);
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}
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c = user_handler(thiscpu->ev, c);
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@ -36,13 +36,14 @@ static void irq_handle(Context *c) {
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}
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static void setup_stack(uintptr_t event, ucontext_t *uc) {
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void *rip = (void *)REG_PC(uc);
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void *pc = (void *)AM_REG_PC(uc);
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extern uint8_t _start, _etext;
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int trap_from_user = __am_in_userspace(rip);
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int signal_safe = IN_RANGE(rip, RANGE(&_start, &_etext)) || trap_from_user ||
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int trap_from_user = __am_in_userspace(pc);
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int signal_safe = IN_RANGE(pc, RANGE(&_start, &_etext)) || trap_from_user ||
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// Hack here: "+13" points to the instruction after syscall. This is the
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// instruction which will trigger the pending signal if interrupt is enabled.
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(rip == (void *)&sigprocmask + 13);
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// FIXME: should change 13 for aarch and riscv
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(pc == (void *)&sigprocmask + 13);
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if (((event == EVENT_IRQ_IODEV) || (event == EVENT_IRQ_TIMER)) && !signal_safe) {
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// Shared libraries contain code which are not reenterable.
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@ -58,17 +59,17 @@ static void setup_stack(uintptr_t event, ucontext_t *uc) {
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if (trap_from_user) __am_pmem_unprotect();
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// skip the instructions causing SIGSEGV for syscall
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if (event == EVENT_SYSCALL) { rip += SYSCALL_INSTR_LEN; }
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REG_PC(uc) = (uintptr_t)rip;
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if (event == EVENT_SYSCALL) { pc += SYSCALL_INSTR_LEN; }
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AM_REG_PC(uc) = (uintptr_t)pc;
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// switch to kernel stack if we were previously in user space
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uintptr_t rsp = trap_from_user ? thiscpu->ksp : REG_SP(uc);
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rsp -= sizeof(Context);
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uintptr_t sp = trap_from_user ? thiscpu->ksp : AM_REG_SP(uc);
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sp -= sizeof(Context);
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#ifdef __x86_64__
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// keep (rsp + 8) % 16 == 0 to support SSE
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if ((rsp + 8) % 16 != 0) rsp -= 8;
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// keep (sp + 8) % 16 == 0 to support SSE
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if ((sp + 8) % 16 != 0) sp -= 8;
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#endif
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Context *c = (void *)rsp;
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Context *c = (void *)sp;
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// save the context on the stack
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c->uc = *uc;
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@ -77,17 +78,17 @@ static void setup_stack(uintptr_t event, ucontext_t *uc) {
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__am_get_intr_sigmask(&uc->uc_sigmask);
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// call irq_handle after returning from the signal handler
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REG_GPR1(uc) = (uintptr_t)c;
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REG_PC(uc) = (uintptr_t)irq_handle;
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REG_SP(uc) = (uintptr_t)c;
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AM_REG_GPR1(uc) = (uintptr_t)c;
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AM_REG_PC(uc) = (uintptr_t)irq_handle;
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AM_REG_SP(uc) = (uintptr_t)c;
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}
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static void iret(ucontext_t *uc) {
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Context *c = (void *)REG_GPR1(uc);
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Context *c = (void *)AM_REG_GPR1(uc);
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// restore the context
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*uc = c->uc;
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thiscpu->ksp = c->ksp;
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if (__am_in_userspace((void *)REG_PC(uc))) __am_pmem_protect();
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if (__am_in_userspace((void *)AM_REG_PC(uc))) __am_pmem_protect();
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}
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static void sig_handler(int sig, siginfo_t *info, void *ucontext) {
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@ -168,8 +169,8 @@ Context* kcontext(Area kstack, void (*entry)(void *), void *arg) {
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Context *c = (Context*)kstack.end - 1;
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__am_get_example_uc(c);
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REG_PC(&c->uc) = (uintptr_t)__am_kcontext_start;
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REG_SP(&c->uc) = (uintptr_t)kstack.end;
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AM_REG_PC(&c->uc) = (uintptr_t)__am_kcontext_start;
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AM_REG_SP(&c->uc) = (uintptr_t)kstack.end;
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int ret = sigemptyset(&(c->uc.uc_sigmask)); // enable interrupt
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assert(ret == 0);
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@ -8,13 +8,17 @@
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#include <klib-macros.h>
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#ifdef __x86_64__
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#define REG_PC(uc) (uc)->uc_mcontext.gregs[REG_RIP]
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#define REG_SP(uc) (uc)->uc_mcontext.gregs[REG_RSP]
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#define REG_GPR1(uc) (uc)->uc_mcontext.gregs[REG_RDI]
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#elif __aarch64__
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#define REG_PC(uc) (uc)->uc_mcontext.pc
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#define REG_SP(uc) (uc)->uc_mcontext.sp
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#define REG_GPR1(uc) (uc)->uc_mcontext.regs[0]
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#define AM_REG_PC(uc) (uc)->uc_mcontext.gregs[REG_RIP]
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#define AM_REG_SP(uc) (uc)->uc_mcontext.gregs[REG_RSP]
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#define AM_REG_GPR1(uc) (uc)->uc_mcontext.gregs[REG_RDI]
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#elif defined(__aarch64__)
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#define AM_REG_PC(uc) (uc)->uc_mcontext.pc
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#define AM_REG_SP(uc) (uc)->uc_mcontext.sp
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#define AM_REG_GPR1(uc) (uc)->uc_mcontext.regs[0]
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#elif defined(__riscv) && __riscv_xlen == 64
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#define AM_REG_PC(uc) (uc)->uc_mcontext.__gregs[REG_PC]
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#define AM_REG_SP(uc) (uc)->uc_mcontext.__gregs[REG_SP]
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#define AM_REG_GPR1(uc) (uc)->uc_mcontext.__gregs[REG_A0]
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#else
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#error Unsupported architecture
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#endif
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@ -19,4 +19,11 @@ __am_kcontext_start:
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and sp, x2, #0xfffffffffffffff0
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br x1
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bl __am_panic_on_return
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#elif __riscv
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// See riscv ABI manual for more details
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// https://github.com/riscv-non-isa/riscv-elf-psabi-doc
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addi sp, sp, -16
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andi sp, sp, ~15
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jalr a1
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jal __am_panic_on_return
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#endif
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@ -124,8 +124,8 @@ Context* ucontext(AddrSpace *as, Area kstack, void *entry) {
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Context *c = (Context*)kstack.end - 1;
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__am_get_example_uc(c);
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REG_PC(&c->uc) = (uintptr_t)entry;
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REG_SP(&c->uc) = (uintptr_t)USER_SPACE.end;
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AM_REG_PC(&c->uc) = (uintptr_t)entry;
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AM_REG_SP(&c->uc) = (uintptr_t)USER_SPACE.end;
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int ret = sigemptyset(&(c->uc.uc_sigmask)); // enable interrupt
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assert(ret == 0);
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