2020 release

am/include/arch/mips32-nemu.h

@@ -0,0 +1,15 @@
+#ifndef __ARCH_H__
+#define __ARCH_H__
+
+struct Context {
+  uintptr_t hi, gpr[32], epc, cause, lo, status;
+  void *pdir;
+};
+
+#define GPR1 gpr[2] // v0
+#define GPR2 gpr[0]
+#define GPR3 gpr[0]
+#define GPR4 gpr[0]
+#define GPRx gpr[0]
+
+#endif

am/include/arch/native.h

@@ -0,0 +1,26 @@
+#ifndef ARCH_H__
+#define ARCH_H__
+
+#ifndef __USE_GNU
+# define __USE_GNU
+#endif
+
+#include <ucontext.h>
+
+struct Context {
+  uintptr_t ksp;
+  void *vm_head;
+  ucontext_t uc;
+  // skip the red zone of the stack frame, see the amd64 ABI manual for details
+  uint8_t redzone[128];
+};
+
+#define GPR1 uc.uc_mcontext.gregs[REG_RDI]
+#define GPR2 uc.uc_mcontext.gregs[REG_RSI]
+#define GPR3 uc.uc_mcontext.gregs[REG_RDX]
+#define GPR4 uc.uc_mcontext.gregs[REG_RCX]
+#define GPRx uc.uc_mcontext.gregs[REG_RAX]
+
+#undef __USE_GNU
+
+#endif

am/include/arch/riscv32-nemu.h

@@ -0,0 +1,15 @@
+#ifndef ARCH_H__
+#define ARCH_H__
+
+struct Context {
+  uintptr_t epc, cause, gpr[32], status;
+  void *pdir;
+};
+
+#define GPR1 gpr[17] // a7
+#define GPR2 gpr[0]
+#define GPR3 gpr[0]
+#define GPR4 gpr[0]
+#define GPRx gpr[0]
+
+#endif

am/include/arch/x86-nemu.h

@@ -0,0 +1,16 @@
+#ifndef ARCH_H__
+#define ARCH_H__
+
+struct Context {
+  uintptr_t esi, ebx, eax, eip, edx, eflags, ecx, cs, esp, edi, ebp;
+  void *cr3;
+  int irq;
+};
+
+#define GPR1 eax
+#define GPR2 eip
+#define GPR3 eip
+#define GPR4 eip
+#define GPRx eip
+
+#endif

am/include/arch/x86-qemu.h

@@ -0,0 +1,17 @@
+#ifndef ARCH_H__
+#define ARCH_H__
+
+struct Context {
+  void    *cr3;
+  uint32_t ds, eax, ebx, ecx, edx,
+           esp0, esi, edi, ebp,
+           eip, cs, eflags, esp, ss3;
+};
+
+#define GPR1 eax
+#define GPR2 ebx
+#define GPR3 ecx
+#define GPR4 edx
+#define GPRx eax
+
+#endif

am/include/arch/x86_64-qemu.h

@@ -0,0 +1,21 @@
+#ifndef ARCH_H__
+#define ARCH_H__
+
+struct Context {
+  void    *cr3;
+  uint64_t rax, rbx, rcx, rdx,
+           rbp, rsi, rdi,
+           r8, r9, r10, r11,
+           r12, r13, r14, r15,
+           rip, cs, rflags,
+           rsp, ss, rsp0;
+};
+
+
+#define GPR1 rdi
+#define GPR2 rsi
+#define GPR3 rdx
+#define GPR4 rcx
+#define GPRx rax
+
+#endif