riscv64-mycpu: pass compilation of am-tests

am/include/arch/riscv64-mycpu.h

@@ -0,0 +1,16 @@
+#ifndef ARCH_H__
+#define ARCH_H__
+
+struct Context {
+  // TODO: fix the order of these members to match trap.S
+  uintptr_t epc, cause, gpr[32], status;
+};
+
+#define GPR1 gpr[0]
+#define GPR2 gpr[0]
+#define GPR3 gpr[0]
+#define GPR4 gpr[0]
+#define GPRx gpr[0]
+
+#endif
+

am/src/mycpu/cte.c

@@ -0,0 +1,45 @@
+#include <am.h>
+#include <klib.h>
+
+static Context* (*user_handler)(Event, Context*) = NULL;
+
+Context* __am_irq_handle(Context *c) {
+  if (user_handler) {
+    Event ev = {0};
+    switch (c->cause) {
+      default: ev.event = EVENT_ERROR; break;
+    }
+
+    c = user_handler(ev, c);
+    assert(c != NULL);
+  }
+
+  return c;
+}
+
+extern void __am_asm_trap(void);
+
+bool cte_init(Context*(*handler)(Event, Context*)) {
+  // initialize exception entry
+  asm volatile("csrw mtvec, %0" : : "r"(__am_asm_trap));
+
+  // register event handler
+  user_handler = handler;
+
+  return true;
+}
+
+Context *kcontext(Area kstack, void (*entry)(void *), void *arg) {
+  return NULL;
+}
+
+void yield() {
+  asm volatile("li a7, -1; ecall");
+}
+
+bool ienabled() {
+  return false;
+}
+
+void iset(bool enable) {
+}

am/src/mycpu/mpe.c

@@ -0,0 +1,17 @@
+#include <am.h>
+
+bool mpe_init(void (*entry)()) {
+  return false;
+}
+
+int cpu_count() {
+  return 1;
+}
+
+int cpu_current() {
+  return 0;
+}
+
+int atomic_xchg(int *addr, int newval) {
+  return 0;
+}

am/src/mycpu/trap.S

@@ -0,0 +1,51 @@
+
+#define concat_temp(x, y) x ## y
+#define concat(x, y) concat_temp(x, y)
+#define MAP(c, f) c(f)
+
+#define REGS(f) \
+      f( 1)       f( 3) f( 4) f( 5) f( 6) f( 7) f( 8) f( 9) \
+f(10) f(11) f(12) f(13) f(14) f(15) f(16) f(17) f(18) f(19) \
+f(20) f(21) f(22) f(23) f(24) f(25) f(26) f(27) f(28) f(29) \
+f(30) f(31)
+
+#define PUSH(n) sd concat(x, n), (n * 8)(sp);
+#define POP(n)  ld concat(x, n), (n * 8)(sp);
+
+#define CONTEXT_SIZE ((32 + 3) * 8)
+#define OFFSET_SP     ( 2 * 8)
+#define OFFSET_CAUSE  (32 * 8)
+#define OFFSET_STATUS (33 * 8)
+#define OFFSET_EPC    (34 * 8)
+
+.globl __am_asm_trap
+__am_asm_trap:
+  addi sp, sp, -CONTEXT_SIZE
+
+  MAP(REGS, PUSH)
+
+  mv t0, sp
+  addi t0, t0, CONTEXT_SIZE
+  sd t0, OFFSET_SP(sp)
+
+  csrr t0, mcause
+  csrr t1, mstatus
+  csrr t2, mepc
+
+  sd t0, OFFSET_CAUSE(sp)
+  sd t1, OFFSET_STATUS(sp)
+  sd t2, OFFSET_EPC(sp)
+
+  mv a0, sp
+  jal __am_irq_handle
+
+  ld t1, OFFSET_STATUS(sp)
+  ld t2, OFFSET_EPC(sp)
+  csrw mstatus, t1
+  csrw mepc, t2
+
+  MAP(REGS, POP)
+
+  addi sp, sp, CONTEXT_SIZE
+
+  mret

am/src/mycpu/vme.c

@@ -0,0 +1,18 @@
+#include <am.h>
+
+bool vme_init(void* (*pgalloc_f)(int), void (*pgfree_f)(void*)) {
+  return false;
+}
+
+void protect(AddrSpace *as) {
+}
+
+void unprotect(AddrSpace *as) {
+}
+
+void map(AddrSpace *as, void *va, void *pa, int prot) {
+}
+
+Context *ucontext(AddrSpace *as, Area kstack, void *entry) {
+  return NULL;
+}

scripts/riscv64-mycpu.mk

@@ -10,7 +10,11 @@ AM_SRCS := mycpu/start.S \
            mycpu/libgcc/div.S \
            mycpu/ioe.c \
            mycpu/timer.c \
-           mycpu/input.c
+           mycpu/input.c \
+           mycpu/cte.c \
+           mycpu/trap.S \
+           mycpu/vme.c \
+           mycpu/mpe.c
 
 CFLAGS    += -fdata-sections -ffunction-sections
 LDFLAGS   += -T $(AM_HOME)/scripts/platform/nemu.ld --defsym=_pmem_start=0x80000000 --defsym=_entry_offset=0x0